53C810 データシートの表示（PDF） - Unspecified

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53C810

PCI-SCSI I/O Processor

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PREUMINARY

Chapter Four

Signal Descriptions

System Pins

Symbol

Pin No.

Type

CLK

80

I

RST

79

I

Address and Data

Symbol

Pin No.

Type

AD(31-0)

1, 2,4, 6, 7, TIS

8, 23, 24, 25,

27, 28, 29, 30,

31, 33, 35, 36,

38, 39, 41, 42,

44, 45, 85, 88,

89, 91, 92, 94,

95, 98, 100

C_BFJ(3-0) 10, 21, 34, 96 TIS

PAR

20

TIS

Description

Clock provides timing for all transactions on the PCI bus and

is an input to every PCI device. All other PCI signals are

sampled on the rising edge of CLK, and other timing

parameters are defined with respect to this edge. This clock can

be optionally used as the SCSI core clock; however, fast SCSI

transfer rates may not be achieved.

Reset forces the PCI sequencer of each device to a known

state. All tis and s/tis signals are forced to a high

impedance state, and all internal logic is reset. The RST input is

synchronized internally to the rising edge of CLK. The CLK

input must be active while RST is active to properly reset

the device.

Description

Physicallongword address and data are multiplexed on the same

PCI pins. During the first clock of a transaction AD (31-0)

contain a physical byte address. During

subsequent clocks, AD(31-0) contain data. A bus

transaction consists of an address phase, followed by one

or more data phases. PCI supports both read and write

bursts. Little Endian byte ordering is used. AD(7-0) define the

least significant byte, and AD(31-24) the most significant byte.

Bus command and byte enables are multiplexed on the same

PCI pins. During the address phase of a transaction, C_BFJ(3-0)

define the bus command. During the data phase, C_BFJ(3-0)

are used as byte enables. The byte enables determine which

byte lanes carry meaningful data. C_BFJ(0) applies to byte 0, and

C_BFJ(3) to, byte 3.

Parity is the even parity bit that protects the AD(31-0) and C_BFJ

(3-0) lines. During address phase, both the address and com-

mand bits are covered. During data phase, both data and byte

enables are covered.

NCR 53C810 Data Manual

4-3

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