53C810 データシートの表示（PDF） - Unspecified

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53C810

PCI-SCSI I/O Processor

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Chapter Three

PCI Functional Description

PRELIMINARY

At initialization time, each PCI device is assigned

a base address (in the case of the 53C810, the

upper 24 bits of the address are selected) for

memory accesses and 110.accesses. On every

access, the 53C810 compares its assigned base

adresses with the value on the AID bus during the

PCI address phase. If there is a match of the

upper 24 bits, the access is for the 53C810 and

the low order 8 bits defme the register to be

accessed. A decode of the CBEI (3-0) determines

which registers and what type of access is to be

performed.

PCI defmes memory space as a contigUous 32-bit

memory address that is shared by all system

resources including the 53C810. Base Address

Register 1 determines which 256-byte memory

area this device will occupy.

PCI defines 110 space as a contiguous 32-bit 110

address that is shared by all system resources,

including the 53C810. Base Address Register 0

determines which 256-byte 110 area this device

will occupy.

PCI Bus Commands

and Functions Supported

Bus commands indicate to the target the type of

transaction the master is requesting. Bus com-

mands are encoded on the C_BEI(3-0) lines

during the address phase. (pCI bus command

encoding and types are listed in Table 3-1.)

The 110 Read command is used to read data from

an agent mapped in 110 address space. All 32

address bits are decoded.

The 110 Write command is used to write data to

an agent when mapped in 110 address space. All

32 address bits are decoded.

The Memory Read command is used to read data

from an agent mapped in memory address space.

All 32 address bits are decoded.

The Memory Write command is used to write

data to an agent when mapped in memory ad-

dress space. All 32 address bits are decoded.

The 53C810 responds to Memory Read Multiple,

Memory Read Line, and Memory Write and

Invalidate commands by treating them similar to

standard Memory Read and Memory Write

commands. The 53C810 will not respond to

reserved commands, special cycle, or interrupt

acknowledge commands.

Configuration Registers

Configuration registers are accessible only by PCI

configuration cycles. No other cycles, including

SCRIPTS, can access these registers.

The lower 128 bytes hold configuration data

while the upper 128 bytes hold the 53C810

operating registers, which are described in Chap-

ter Five, Operating Registers. These registers can

be accessed by SCRIPTS.

Table 3-2 depicts the PCI configuration data

implemented by the 53C810. Note that addresses

40h through 7Fh are not defined.

All PCI-compliant devices, such as the 53C81 0,

must support the Vendor ID, Device ID, Com-

mand, and Status Registers. Support of other

PCI-compliant registers is optional. In the

53C810, registers that are not supported are not

writable and will return all zeroes when read.

Only those registers and bits that are currently

supported by the 53C810 are described in this

chapter. For more detailed information on PCI

registers, please see the PCI Specification.

3-2

NCR 53C81 0 Data Manual

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