EP2C50AU208I7ES データシートの表示（PDF） - Altera Corporation

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EP2C50AU208I7ES

Section I. Cyclone II Device Family Data Sheet

Altera Corporation 

Embedded Multipliers

Figure 2–17. M4K RAM Block LAB Row Interface

C4 Interconnects

Direct link

16

interconnect

to adjacent LAB

dataout

Direct link

16

interconnect

from adjacent LAB

M4K RAM

Block

Byte enable

Clocks

Control

Signals

address datain

R4 Interconnects

Direct link

interconnect

to adjacent LAB

16 Direct link

interconnect

from adjacent LAB

6

M4K RAM Block Local

Interconnect Region

LAB Row Clocks

f

For more information on Cyclone II embedded memory, see the

Cyclone II Memory Blocks chapter in Volume 1 of the Cyclone II Device

Handbook.

Embedded

Multipliers

Cyclone II devices have embedded multiplier blocks optimized for

multiplier-intensive digital signal processing (DSP) functions, such as

finite impulse response (FIR) filters, fast Fourier transform (FFT)

functions, and discrete cosine transform (DCT) functions. You can use the

embedded multiplier in one of two basic operational modes, depending

on the application needs:

■ One 18-bit multiplier

■ Up to two independent 9-bit multipliers

2–32

Cyclone II Device Handbook, Volume 1

Altera Corporation

February 2007

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