CY7C1486BV25-250BGXI データシートの表示（PDF） - Cypress Semiconductor

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CY7C1486BV25-250BGXI

72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

Cypress Semiconductor 

CY7C1480BV25

CY7C1482BV25, CY7C1486BV25

SAMPLE/PRELOAD instruction. If this is an issue, it is still

possible to capture all other signals and simply ignore the value

of the CLK captured in the boundary scan register.

After the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the boundary

scan register between the TDI and TDO balls.

Note that because the PRELOAD part of the command is not

implemented, putting the TAP to the Update-DR state while

performing a SAMPLE/PRELOAD instruction has the same

effect as the Pause-DR command.

Figure 4. TAP Timing

1

2

BYPASS

When the BYPASS instruction is loaded in the instruction register

and the TAP is placed in a Shift-DR state, the bypass register is

placed between the TDI and TDO balls. The advantage of the

BYPASS instruction is that it shortens the boundary scan path

when multiple devices are connected together on a board.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

3

4

5

6

Test Clock

(TCK)

Test Mode Select

(TMS)

t TH

tTL

tTMSS tTMSH

t CYC

t TDIS

t TDIH

Test Data-In

(TDI)

t TDOV

Test Data-Out

(TDO)

t TDOX

DON’T CARE

UNDEFINED

TAP AC Switching Characteristics

Over the Operating Range[9, 10]

Parameter

Description

Min

Clock

tTCYC

TCK Clock Cycle Time

50

tTF

TCK Clock Frequency

tTH

TCK Clock HIGH Time

20

tTL

TCK Clock LOW Time

20

Output Times

tTDOV

TCK Clock LOW to TDO Valid

tTDOX

TCK Clock LOW to TDO Invalid

0

Setup Times

tTMSS

TMS Setup to TCK Clock Rise

5

tTDIS

TDI Setup to TCK Clock Rise

5

tCS

Capture Setup to TCK Rise

5

Hold Times

tTMSH

TMS Hold after TCK Clock Rise

5

tTDIH

TDI Hold after Clock Rise

5

tCH

Capture Hold after Clock Rise

5

Notes

9. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

10. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.

Max

20

10

Unit

ns

MHz

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Document #: 001-15143 Rev. *D

Page 14 of 31

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