QL12X16B データシートの表示（PDF） - Unspecified

部品番号

コンポーネント説明

メーカー

QL12X16B

Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA

Unspecified 

Military 5.0V pASIC 1 Family

Symbol

tIN

tINI

Parameter

High Drive Input Delay

High Drive Input,

Inverting Delay

High Drive Buffer

Clock Drivers

Wired Together

1

2

3

4

1

2

3

4

Propagation Delays (ns) [4]

Fanout

12 24 48 72 96

5.8 7.2

5.0 7.1

5.8 6.7 7.7

5.9 6.8

6.0 7.4

5.2 7.3

6.0 6.9 7.9

6.1 7.0

[4] Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA =

25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature set-

tings as specified in the Operating Range.

AC Performance

Propagation delays depend on routing, fanout, load

capacitance, supply voltage, junction temperature,

and process variation. The AC Characteristics are a

design guide to provide initial timing estimates at

nominal conditions. Worst case estimates are

obtained when nominal propagation delays are multi-

plied by the appropriate Delay Factor, K, as specified

in the Delay Factor table (Operating Range). The

effects of voltage and temperature variation are illus-

trated in the graphs on the following pages, K Factor

versus Voltage and Temperature. The pASIC Devel-

opment Tools incorporate data sheet AC Character-

istics into the QDIF database for pre-place-and-route

timing analysis. The SpDE Delay Modeler extracts

specific timing parameters for precise path analysis

or simulation results following place and route.

ORDERING INFORMATION

QuickLogic

pASIC device

QL 24x32B - 1 CF208 M

Operating Range

M = Military

M/883C = MIL STD 883

pASIC device part number

B = 0.65 micron CMOS

8x12B

12x16B

16x24B

24x32B

Speed Grade

0 = fast

1 = faster

Package Code

CG68 = 68-pin CPGA

CG84 = 84-pin CPGA

CG144 = 144-pin CPGA

CF160 = 160-pin CQFD

PQ208 = 208-pin PQFP

CF208 = 208-pin CQFP

8-22

22

Preliminary

Share Link: