MT48LC16M16A2F4-7E データシートの表示（PDF） - Micron Technology

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MT48LC16M16A2F4-7E

256Mb: x4, x8, x16 SDRAM

Micron Technology 

256Mb: x4, x8, x16 SDRAM

PRECHARGE Operation

Figure 51: Single WRITE Without Auto Precharge

T0

CLK

tCKS tCKH

CKE

Command

tCMS tCMH

ACTIVE

DQM

Address

A10

BA0, BA1

tAS tAH

Row

tAS tAH

Row

tAS tAH

Bank

DQ

T1

tCK

NOP

T2

tCL

tCH

WRITE

tCMS tCMH

Column m

Disable auto precharge

Bank

tDS tDH

DIN

T3

NOP

T4

T5

T6

T7

T8

NOP

PRECHARGE

NOP

ACTIVE

NOP

All banks

Single bank

Bank

Row

Bank

tRCD

tRAS

tRC

tWR

tRP

Don’t Care

Note: 1. For this example, BL = 1 and the WRITE burst is followed by a manual PRECHARGE.

PDF: 09005aef8091e6d1

256Mb_sdr.pdf - Rev. S 12/12 EN

78

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© 1999 Micron Technology, Inc. All rights reserved.

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