256Mb: x4, x8, x16 SDRAM
PRECHARGE Operation
Figure 48: WRITE With Auto Precharge
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
tCK
tCKS tCKH
tCL
tCH
CKE
tCMS tCMH
Command
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
DQM
tCMS tCMH
Address
A10
BA0, BA1
tAS tAH
Row
tAS tAH
Row
tAS tAH
Bank
Column m
Enable auto precharge
Bank
Row
Row
Bank
tDS tDH
tDS tDH
tDS tDH
tDS tDH
DQ
DIN
DIN
DIN
DIN
tRCD
tRAS
tWR
tRP
tRC
Don’t Care
Note: 1. For this example, BL = 4.
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. S 12/12 EN
75
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