MT48LC16M16A2P-75(2005) データシートの表示（PDF） - Micron Technology

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MT48LC16M16A2P-75
(Rev.:2005)

256Mb: x4, x8, x16 SDRAM

Micron Technology 

256Mb: x4, x8, x16

SDRAM

Figure 14: Random READ Accesses

T0

T1

T2

T3

CLK

T4

T5

COMMAND

READ

READ

READ

READ

NOP

NOP

ADDRESS

BANK,

COL n

BANK,

COL a

BANK,

COL x

BANK,

COL m

DQ

CAS Latency = 2

DOUT

n

DOUT

a

DOUT

x

DOUT

m

T0

T1

T2

T3

T4

T5

T6

CLK

COMMAND

READ

READ

READ

READ

NOP

NOP

NOP

ADDRESS

BANK,

COL n

BANK,

COL a

BANK,

COL x

BANK,

COL m

DQ

DOUT

n

DOUT

a

DOUT

x

DOUT

m

CAS Latency = 3

TRANSITIONING DATA

DON’T CARE

NOTE: Each READ command may be to any bank. DQM is LOW.

PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8

256MSDRAM.pmd – Rev. H; Pub. 2/05

21

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2003 Micron Technology, Inc. All rights reserved.

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