MT48LC16M16A2P-75(2005) データシートの表示（PDF） - Micron Technology

部品番号

コンポーネント説明

メーカー

MT48LC16M16A2P-75
(Rev.:2005)

256Mb: x4, x8, x16 SDRAM

Micron Technology 

valid, where x equals the CAS latency minus one.

This is shown in Figure 13 for CAS latencies of two and

three; data element n + 3 is either the last of a burst of

four or the last desired of a longer burst. The 256Mb

SDRAM uses a pipelined architecture and therefore

does not require the 2n rule associated with a prefetch

256Mb: x4, x8, x16

SDRAM

architecture. A READ command can be initiated on any

clock cycle following a previous READ command. Full-

speed random read accesses can be performed to the

same bank, as shown in Figure 14, or each subsequent

READ may be performed to a different bank.

T0

CLK

Figure 13: Consecutive READ Bursts

T1

T2

T3

T4

T5

T6

COMMAND

READ

NOP

NOP

NOP

READ

NOP

NOP

ADDRESS

BANK,

COL n

X = 1 cycle

BANK,

COL b

DQ

CAS Latency = 2

DOUT

n

DOUT

n+1

DOUT

n+2

DOUT

n+3

DOUT

b

T0

T1

T2

T3

T4

T5

T6

T7

CLK

COMMAND

READ

NOP

NOP

NOP

READ

NOP

NOP

NOP

ADDRESS

BANK,

COL n

DQ

CAS Latency = 3

BANK,

COL b

X = 2 cycles

DOUT

n

DOUT

n+1

DOUT

n+2

DOUT

n+3

DOUT

b

TRANSITIONING DATA

DON’T CARE

NOTE: Each READ command may be to any bank. DQM is LOW.

PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8

256MSDRAM.pmd – Rev. H; Pub. 2/05

20

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2003 Micron Technology, Inc. All rights reserved.

Share Link: