MT47H128M8SH-187EITM データシートの表示（PDF） - Micron Technology

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MT47H128M8SH-187EITM

1Gb: x4, x8, x16 DDR2 SDRAM

Micron Technology 

1Gb: x4, x8, x16 DDR2 SDRAM

WRITE

Figure 64: Bank Write – Without Auto Precharge

CK#

T0

T1

T2

T3

T4

T5 T5n T6 T6n T7

T8

T9

CK

tCK

tCH tCL

CKE

Command

NOP1

ACT

NOP1

WRITE2

NOP1

NOP1

NOP1

NOP1

NOP1

PRE

Address

A10

Bank select

DQS, DQS#

DQ6

DM

RA

RA

Bank x

tRCD

Col n

3

Bank x

WL = 2

WL ±tDQSS (NOM)

tRAS

5

tWPRE

DnI

tDQSL tDQSH tWPST

tWR

All banks

One bank

Bank x4

tRP

Transitioning Data

Don’t Care

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at

these times.

2. BL = 4 and AL = 0 in the case shown.

3. Disable auto precharge.

4. “Don’t Care” if A10 is HIGH at T9.

5. Subsequent rising DQS signals must align to the clock within tDQSS.

6. DI n = data-in for column n; subsequent elements are applied in the programmed order.

7. tDSH is applicable during tDQSS (MIN) and is referenced from CK T5 or T6.

8. tDSS is applicable during tDQSS (MAX) and is referenced from CK T6 or T7.

PDF: 09005aef8565148a

1GbDDR2.pdf – Rev. AA 07/14 EN

110

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