ADVANCE
512Mb: x4, x8, x16
DDR SDRAM
CK#
CK
COMMAND
ADDRESS
DQS
DQ
T0
READ
Bank,
Col n
T1
NOP
CL = 2
T2 T2n T3 T3n T4 T4n T5 T5n
READ
NOP
NOP
NOP
Bank,
Col b
DO
DO
n
b
CK#
CK
COMMAND
ADDRESS
T0
READ
Bank,
Col n
T1
T2 T2n T3 T3n T4 T4n T5 T5n
NOP
READ
NOP
NOP
NOP
CL = 2.5
Bank,
Col b
DQS
DQ
DO
DO
n
b
DON’T CARE
TRANSITIONING DATA
NOTE: 1. DO n (or b) = data-out from column n (or column b).
2. Burst length = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first).
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Three (or seven) subsequent elements of data-out appear in the programmed order following DO b.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.
6. Example applies only when READ commands are issued to same device.
Figure 8
Consecutive READ Bursts
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65 – Rev. B; Pub 4/01
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©2001, Micron Technology, Inc.