MAX1463 データシートの表示（PDF） - Maxim Integrated
部品番号
コンポーネント説明
メーカー
MAX1463 Datasheet PDF : 50 Pages
| |||
Low-Power Two-Channel Sensor
Signal Processor
flict in switch activation, a priority is applied to the switch
logic to prevent the conflict.
The DAC and/or the PWM can be selected as the out-
put signal source. The DAC output signal is routed to
one of the op amps and made available to a device
pin. Selecting the large op amp as the DAC output dri-
ver device enables a robust current drive capability for
driving signals into low-impedance loads or across
long lengths of wire. The unity-gain buffer configuration
is automatically selected, and it provides the DAC out-
put signal directly to the device pin OUTnLG. With the
large op amp selected, the small op amp can be used
as an independent device for external circuit applica-
tions when the PWM is disabled. Alternatively, the PWM
can also be enabled to drive the OUTnSM device pin,
in which case the small op amp is OFF.
Selecting the small op amp as the DAC output driver
device is useful for routing the output signal to other cir-
cuits in an embedded control system with high-imped-
ance load connections. The unity-gain buffer configuration
is automatically selected, and it provides the DAC output
signal directly to the device pin OUTnSM. With the small
op amp selected, the large op amp can be used as an
independent device for external circuit applications when
the PWM is disabled. Alternatively, the PWM can also be
enabled to drive the OUTnLG device pin, in which case
the large op amp is OFF.
The DAC has two reference voltage sources available
by selection, VDD and VREF pin. When the external ref-
erence is selected (VREF), the actual DAC reference is
2 x VREF. This allows for some degree of flexibility in the
bit weight of the DAC. The output of the DAC is a volt-
age proportional to the reference voltage selected,
where the proportionality scaling (DAC input) is set in
the data input register DOPn_Data.
The DOP module also provides a 12-bit digital PWM
output. At a nominal frequency of 4MHz, the frequency
of the PWM is 122Hz (PWM period = 8.192ms). The
DAC and the PWM share the same input register,
DOPn_Data, where the PWM uses the 12 MSBs, in
two’s-complement format. An input of 000Xh (4 LSBs
are ignored) outputs a 50% duty cycle waveform at the
selected output pin (either OUTnSM or OUTnLG). The
PWM bit weight is 2µs, at a nominal frequency of 4MHz.
The minimum duty cycle is obtained when the input is
800Xh (duty cycle is 0 / 4096 = 0), and the maximum
duty cycle at 7FFXh (duty cycle is 4095 / 4096 =
99.98%). A new PWM input word is only effective at the
end of a current PWM cycle, therefore preventing PWM
glitches on the output.
Either the small or the large op amp in the DOP module
can also be selected as an uncommitted op amp in the
MAX1463. The op amps can be configured as a unity-
gain buffer, where the output is internally connected to the
negative terminal of the op amp, or a stand-alone op amp,
where both AMPnM and AMPnP can be externally con-
nected for various analog functions. In the case of a
buffer, the device pin AMPnM is in high-impedance mode,
as the feedback loop around the op amp is connected
internally.
Every function of the DOP module can be selected individ-
ually (DAC, PWM, or op amp), or two out of the three func-
tions of the DOP module can be selected at the same time
(PWM and op amp, or DAC and PWM, or DAC and op
amp), as there are only two output pins for the module,
OUTnSM and OUTnLG. The various configuration options
for the DOP are shown in Table 21. The PWRDAC and
PWROP bits are in the power-on control register (address
= 31h), and the remaining bits are in the DOP registers.
See Tables 21 through 27.
Timer Module
The timer module (Figure 6) comprises a 12-bit counter, a
4-bit prescalar, and control and configuration registers.
When the timer is enabled and initiated, the system master
clock, MCLK, is prescaled by the divisor set by PS[3:0] in
the TMR_Config register and the result applied to the 12-
bit upcounter. When the counter value matches the time-
out value TO[11:0] in register TMR_Config, bit TMDN is set
to 1. The CPU can poll the timer done bit TMDN to check
its status.
The timer module provides a feature that enables the CPU
to be put into a low-power halt mode for the duration of the
timer interval. Setting the ENAHALT bit in the TMR_Control
register while starting the timer (setting the timer enable bit
TMEN to 1), or while the timer is already enabled and
counting halts the CPU at the present instruction until the
TMDN bit becomes set by the counter. The CPU com-
mences execution with the next instruction. All CPU regis-
ters and ports are fully static and retain all data during the
elapsed time interval.
The time interval between TMEN being set to 1, and
TMDN being set to 1 can be computed as follows:
Time Interval = (2 / fOSC) x {(prescale value N)
x (timeout value TO[11:0]) + 1.5}
The maximum time interval given fOSC = 4MHz clock is
786ms.
18 ______________________________________________________________________________________
Share Link: 