674R-01 データシートの表示（PDF） - Integrated Circuit Systems
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674R-01 Datasheet PDF : 6 Pages
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PRELIMINARY INFORMATION
ICS674-01
User Configurable Divider
Parameter
Conditions
Minimum Typical
ABSOLUTE MAXIMUM RATINGS (stresses be ond these can permanentl damage the device)
Supply Voltage, VDD
Referenced to GND
Inputs
Referenced to GND
-0.5
Clock Output
Referenced to GND
-0.5
Ambient Operating Temperature
0
Ambient Operating Temperature
I version
-40
Soldering Temperature
Max of 10 seconds
Storage Temperature
-65
DC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Operating Voltage, VDD
3
Input High Voltage, VIH
All A, B, and S pins
2
Input Low Voltage, VIL
All A, B, and S pins
Input High Voltage, VIH, INA and INB only
(VDD/2)+1 VDD/2
Input Low Voltage, VIL, INA and INB only
VDD/2
Output High Voltage, VOH
IOH=-25mA
2.4
Output Low Voltage, VOL
IOL=25mA
IDD, Op. Supply Cur., DivA=DivB=20 at 3.3 V No Load, fin=100 MHz
3
IDD, Op. Supply Cur., DivA=DivB=20 at 5 V
No Load, fin=100 MHz
5
Short Circuit Current, outputs
±70
On-Chip Pull-up Resistor
A, B, S select pins
270
Input Capacitance
A, B, S select pins
5
AC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Input Frequency, Divider A
at 3.3 V
0
Input Frequency, Divider B
at 3.3 V
0
Input Frequency, Divider A
at 5 V
0
Input Frequency, Divider B
at 5 V
0
Input Frequency, Divider A (Industrial temperature) at 3.3 V at 85 °C
0
Input Frequency, Divider B (Industrial temperature) at 3.3 V at 85 °C
0
Input Frequency, Divider A (Industrial temperature) at 5 V at 85 °C
0
Input Frequency, Divider B (Industrial temperature) at 5 V at 85 °C
0
Output Clock Rise Time
0.8 to 2.0V
1
Output Clock Fall Time
2.0 to 0.8V
1
OUTB Clock Duty Cycle (see note)
at VDD/2
45
49 to 51
OUTB Clock Duty Cycle, odd post dividers
at VDD/2, except PD=1
40
OUTA Clock Duty Cycle (see note)
at VDD/2
20
Maximum Units
7
V
VDD+0.5 V
VDD+0.5 V
70
°C
85
°C
260
°C
150
°C
5.5
V
V
0.8
V
V
(VDD/2)-1 V
V
0.4
V
mA
mA
mA
kΩ
pF
135
MHz
180
MHz
200
MHz
235
MHz
125
MHz
170
MHz
190
MHz
220
MHz
ns
ns
55
%
60
%
98.5
%
Note:
The duty cycle of OUTA is dependent on the selected divide. This is because OUTA goes low for 2 input
clock cycles on INA. So, for example, if a divide of 20 is selected, the duty cycle will be 90%.
Similarly, if PD=1 is selected for OUTB, the duty cycle will be dependent on the selected divide. In this
case OUTB goes high for approximately 8 input clock cycles on INB.
MDS 674-01 A
5
Revision 033199
Printed 11/15/00
Integrated Circuit Systems • 525 Race Street • San Jose • CA • 95126 •(408)295-9800tel•(408)295-9818fax
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