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AD9260(2000) データシートの表示(PDF) - Analog Devices

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AD9260 Datasheet PDF : 36 Pages
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AD9260
499
VIN
499
+5V
AD8138
50
CS
100pF
VINA
AD9260
499
499
50
CS
100pF
10F
0.1F
VINB
VREF
Figure 57. AD8138 Single-Ended Differential ADC Driver
The second driver circuit, shown in Figure 58, can provide slightly
enhanced noise performance relative to the AD8138, assuming
low-noise, high-speed op amps are used. This differential op amp
driver circuit is configured to convert and level-shift a 2 V p-p
single-ended, ground-referenced signal to a 4 V p-p differential
signal centered at the common-mode level of the AD9260. The
circuit is based on two op amps that are configured as matched
unity gain difference amplifiers. The single-ended input signal is
applied to opposing inputs of the difference amplifiers, thus
providing differential outputs. The common-mode offset voltage
is applied to the noninverting resistor leg of each difference ampli-
fier providing the required offset voltage. This offset voltage is
derived from the common-mode level (CML) pin of the AD9260
via a low output impedance buffer amplifier capable of driving a
1 µF capacitive load. The common-mode offset can be varied
over a 1.8 V to 2.5 V span without any serious degradation in
distortion performance as shown in Figure 44, thus providing
some flexibility in improving output compression distortion from
some ± 5 op amps with limited positive voltage swing.
To protect the AD9260 from an undervoltage fault condition
from op amps specified for ± 5 V operation, two 50 series
resistors and a diode to AGND are inserted between each op
amp output and the AD9260 inputs. The AD9260 will inherently
be protected against any overvoltage condition if the op amps
share the same positive power supply (i.e., AVDD) as the AD9260.
Note, the gain accuracy and common-mode rejection of each dif-
ference amplifier in this driver circuit can be enhanced by using
a matched thin-film resistor network (i.e., Ohmtek ORNA5000F)
for the op amps. Resistor values should be 500 or less to main-
tain the lowest possible noise.
The noise performance of each unity gain differential driver
circuit is limited by its inherent noise gain of two. For unity gain
op amps ONLY, the noise gain can be reduced from two to one
R
R
VCML-VIN
50
50
R
R
CC
VIN
100pF
CF
VCML-VIN
R
CF
50
CD
100pF
50
R
CC
100pF
R
R
AD817
0.1F
1.0F
VINA
AD9260
VINB
CML
Figure 58. DC-Coupled Differential Driver with
Level-Shifting
beyond the input signals passband by adding a shunt capacitor,
CF, across each op amps feedback resistor. This will essentially
establish a low-pass filter which reduces the noise gain to one
beyond the filters f3 dB while simultaneously bandlimiting the
input signal to f3 dB. Note, the pole established by this filter can
also be used as the real pole of an antialiasing filter. Since the
noise contribution of two op amps from the same product family
are typically equal but uncorrelated, the total output-referred
noise of each op amp will add root-sum square leading to a
further 3 dB degradation in the circuits noise performance.
Further out-of-band noise reduction can be realized with the
addition of single-ended and differential capacitors, CS and CD.
The distortion and noise performance of the two op amps
within the signal path are critical in achieving the AD9260s
optimum performance. Low noise op amps capable of providing
greater than 85 dB THD at 1 MHz while swinging over a 1 V to
3 V range are a rare commodity, yet should only be considered.
The AD9632 op amp was found to provide superb distortion
performance in this circuit due to its ability to maintain excel-
lent distortion performance over a wide bandwidth while swing-
ing over a 1 V to 3 V range. Since the AD9632 is gain-of-two or
greater stable, the use of the noise reduction shunt capacitors
discussed above was prohibited thus degrading its noise perfor-
mance slightly (1 dB2 dB) when compared to the OPA642.
Note, the majority of the AD9260 test and characterization data
presented in this data sheet was taken using the AD9632 op
amp in this dc coupled driver circuit. This driver circuit is also
provided on the AD9260 evaluation board since the AD8138
was unreleased at that time.
Reference
Operating Mode
INTERNAL
INTERNAL
INTERNAL
EXTERNAL
Table IV. Reference Configuration Summary
Input Span (VINAVINB)
(V p-p)
1.6
4.0
1.6 SPAN 4.0 and
SPAN = 1.6 × VREF
1.6 SPAN 4.0
Required VREF
(V)
1
2.5
1 VREF 2.5 and
VREF = (1+R1/R2)
1 VREF 2.5
Connect
SENSE
SENSE
R1
R2
SENSE
VREF
To
VREF
REFCOM
VREF and SENSE
SENSE and REFCOM
AVDD
EXT. REF.
REV. B
–23–

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