ADG466BN データシートの表示（PDF） - Analog Devices

部品番号

コンポーネント説明

メーカー

ADG466BN

Triple and Octal Channel Protectors

Analog Devices 

ADG466/ADG467

CIRCUIT INFORMATION

Figure 17 below shows a simplified schematic of a channel

protector circuit. The circuit is made up of four MOS transis-

tors—two NMOS and two PMOS. One of the PMOS devices

does not lie directly in the signal path but is used to connect the

source of the second PMOS device to its backgate. This has the

effect of lowering the threshold voltage and so increasing the

input signal range of the channel for normal operation. The

source and backgate of the NMOS devices are connected for the

same reason. During normal operation the channel protectors

have a resistance of 60 Ω typ. The channel protectors are very

low power devices, and even under fault conditions the supply

current is limited to sub microampere levels. All transistors are

dielectrically isolated from each other using a trench isolation

method. This makes it impossible to latch up the channel

protectors. For an explanation, see Trench Isolation section.

VSS

NMOS

PMOS

NMOS

VDD

PMOS

VSS

VDD

Figure 17. The Channel Protector Circuit

Overvoltage Protection

When a fault condition occurs on the input of a channel protec-

tor, the voltage on the input has exceeded some threshold volt-

age set by the supply rail voltages. The threshold voltages are

related to the supply rails as follows. For a positive overvoltage,

the threshold voltage is given by VDD – VT where VTN is the

threshold voltage of the NMOS transistor (1.5 V typ). In the

case of a negative overvoltage the threshold voltage is given by

VSS – VTP where VTP is the threshold voltage of the PMOS de-

vice (2 V typ). If the input voltage exceeds these threshold volt-

ages, the output of the channel protector (no load) is clamped at

these threshold voltages. However, the channel protector output

will clamp at a voltage that is inside these thresholds if the out-

put is loaded. For example with an output load of 1 kΩ, VDD =

15 V and a positive overvoltage. The output will clamp at VDD –

VTN – ∆V = 15 V – 1.5 V – 0.6 V = 12.9 V where ∆V is due to I

× R voltage drop across the channels of the MOS devices (see

Figure 19). As can be seen from Figure 19, the current during

fault condition is determined by the load on the output (i.e.,

VCLAMP/RL ). However, if the supplies are off, the fault current is

limited to the nano-ampere level.

Figures 18, 20 and 21 show the operating conditions of the

signal path transistors during various fault conditions. Figure 18

shows how the channel protectors operate when a positive over-

voltage is applied to the channel protector.

VDD – VTN*

(+13.5V)

POSITIVE

OVERVOLTAGE

(+20V)

NMOS

PMOS

SATURATED

NON-

SATURATED

VDD (+15V)

VSS (–15V)

*VTN = NMOS THRESHOLD VOLTAGE (+1.5V)

NMOS

NON-

SATURATED

VDD (+15V)

Figure 18. Positive Overvoltage on the Channel Protector

The first NMOS transistor goes into a saturated mode of opera-

tion as the voltage on its Drain exceeds the Gate voltage (VDD) –

the threshold voltage (VTN). This situation is shown in Figure

19. The potential at the source of the NMOS device is equal to

VDD – VTN. The other MOS devices are in a nonsaturated mode of

operations.

VD

VG

VS

⌬V

(+20V)

(VDD =15V)

(+13.5V)

OVERVOLTAGE

OPERATION

(SATURATED)

N+

N CHANNEL N +

N+

EFFECTIVE

SPACE CHARGE

REGION

VT = 1.5V P –

(VG – VT = 13.5V)

PMOS

NMOS

NONSATURATED

OPERATION

IOUT

VCLAMP

RL

Figure 19. Positive Overvoltages Operation of the Channel Protector

REV. A

–7–

Share Link: