AD7394AN データシートの表示（PDF） - Analog Devices
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コンポーネント説明
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AD7394AN Datasheet PDF : 12 Pages
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AD7394/AD7395
SDI
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CLK
CS
LDA,B
tCSS
tLD1
tCSH
tLD2
SDI
CLK
LDA,B
RS
FS
VOUT
ZS
tDS tDH
tCL
tCH
tLDW
tS
tCLRW
tS
؎1 LSB
ERROR BAND
Figure 2. Timing Diagram
SHDN
IDD
tSDR
Figure 3. Timing Diagram
CS CLK RS
MSB
SHDN
Table I. Control Logic Truth Table
LDA/B Serial Shift Register Function
DAC Register Function
HX
HX
H
H
No Effect
Latched
LL
HX
H
H
No Effect
Latched
LH H X
H
H
No Effect
Latched
L ↑+ H X
H
H
Shift-Register-Data Advanced One Bit Latched
L ↑+ H X
H
L
Shift-Register-Data Advanced One Bit Transparent
LH H X
H
L
No Effect
Transparent
↑+ L
HX
H
H
No Effect
Latched
HX
HX
H
↓–
No Effect
Updated with Current Shift Register
Contents
HX
HX
H
L
No Effect
Transparent
XX
LH
H
X
XX
↑+ H
H
H
XX
LL
H
X
No Effect
No Effect
No Effect
Loaded with 800H
Latched with 800H
Loaded with All Zeros
XX
↑+ L
H
H
No Effect
Latched All Zeros
XX
XX
L
X
No Effect
No Affect
NOTES
1. ↑+ positive logic transition; ↓– negative logic transition; X Don’t Care
2. Do not clock in serial data while level sensitive inputs LDA or LDB are logic LOW.
–4–
REV. 0
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