MAX194BEWE データシートの表示（PDF） - Maxim Integrated

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MAX194BEWE

14-Bit, 85ksps ADC with 10µA Shutdown

Maxim Integrated 

14-Bit, 85ksps ADC with 10µA Shutdown

CS, CONV

CLK

EOC

DOUT

B13 FROM PREVIOUS

CONVERSION

B13

B12

B0

S1 S0

B13

tDV

tCD

tDH

DATA LATCHED:

Figure 18. Timing Diagram for Circuit of Figure 17

QSPI

PCS0

SCK

MISO

GPT OC3

IC1

OC2

IC3

START

1.3µs

MAX194

CS

SCLK

DOUT

BP/UP/SHDN

EOC

RESET

CONV

CLK

74HC32

1.7MHz

Figure 19. MAX194 Connection to QSPI Processor Clocking

Data Out with SCLK Between Conversions

MicroWire is a trademark of National Semiconductor Corp.

Data is clocked out of the MAX194 on CLK’s falling

edge and can be clocked into the µP on the rising

edge or the following falling edge. If you clock data in

on the rising edge (SPI/QSPI with CPOL = 0 and CPHA

= 0; standard MicroWire™: Hitachi H8), the maximum

CLK rate is given by:

fCLK(max)

=

1/ 2

•



 tCD

1

+



tSD 

where tCD is the MAX194’s CLK-to-DOUT valid delay

and tSD is the data setup time for your µP.

If clocking data in on the falling edge (CPOL = 0,

CPHA = 1), the maximum CLK rate is given by:

fCLK(max)

=

1

tCD + tSD

Do not exceed the maximum CLK frequency given in

the Electrical Characteristics table. To clock data in on

the falling edge, your processor hold time must not

exceed tCD minimum (100ns).

While QSPI can provide the required 20 CLK cycles as

two continuous 10-bit transfers, SPI is limited to 8-bit

transfers. This means that with SPI, a conversion must

consist of three 8-bit transfers. Ensure that the pauses

between 8-bit operations at your selected clock rate

are short enough to maintain a 20ms or shorter conver-

sion time, or the leakage of the capacitive DAC may

cause errors.

______________________________________________________________________________________ 17

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