Philips Semiconductors
Quadruple D-type register with 3-state outputs
Product specification
HEF4076B
MSI
FUNCTION TABLE
Notes
INPUTS
OUTPUTS
1. EO0 = EO1 = LOW
When either EO0 or EO1 is HIGH, the outputs are
MR
CP
ED0 ED1
Dn
On
disabled (high impedance OFF-state).
H
X
X
X
X
L
L
H
X
X no change
H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
L
X
H
X no change
= positive-going transition
L
L
L
H
H
= negative-going transition
L
L
L
L
L
L
X
X
X no change
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns; see also waveforms Fig.4
VDD
V
SYMBOL MIN. TYP. MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
CP → On
HIGH to LOW
LOW to HIGH
MR → On
HIGH to LOW
Output transition times
HIGH to LOW
LOW to HIGH
3-state propagation times
Output disable times
EOn → On
HIGH
LOW
5
10
tPHL
15
5
10
tPLH
15
5
10
tPHL
15
5
10
tTHL
15
5
10
tTLH
15
5
10
tPHZ
15
5
10
tPLZ
15
150
305 ns
123 ns + (0,55 ns/pF) CL
60
120 ns
49 ns + (0,23 ns/pF) CL
45
85 ns
37 ns + (0,16 ns/pF) CL
160
320 ns
133 ns + (0,55 ns/pF) CL
65
130 ns
54 ns + (0,23 ns/pF) CL
45
90 ns
37 ns + (0,16 ns/pF) CL
95
190 ns
68 ns + (0,55 ns/pF) CL
40
85 ns
29 ns + (0,23 ns/pF) CL
30
65 ns
22 ns + (0,16 ns/pF) CL
60
120 ns
10 ns + (1,0 ns/pF) CL
30
60 ns
9 ns + (0,42 ns/pF) CL
20
40 ns
6 ns + (0,28 ns/pF) CL
60
120 ns
10 ns + (1,0 ns/pF) CL
30
60 ns
9 ns + (0,42 ns/pF) CL
20
40 ns
6 ns + (0,28 ns/pF) CL
50
105 ns
35
70 ns
30
65 ns
45
90 ns
30
65 ns
30
60 ns
January 1995
4