SMS8198 データシートの表示（PDF） - Summit Microelectronics

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SMS8198

Philips TriMedia™ Processor Companion Supervisor With a 16K-bit 2-wire Serial Memory

Summit Microelectronics 

SMS8198

WRITE OPERATIONS

The SMS8198 allows two types of write operations: byte

write and page write. The byte write operation writes a

single byte during the nonvolatile write period (tWR). The

page write operation allows up to 16 bytes in the same

page to be written during tWR.

Byte WRITE

After the slave address is sent (to identify the slave

device, specify high order word address and a read or

write operation), a second byte is transmitted which

contains the low 8 bit addresses of any one of the 2,048

words in the array.

Upon receipt of the word address, the SMS8198 re-

sponds with an ACKnowledge. After receiving the next

byte of data, it again responds with an ACKnowledge. The

master then terminates the transfer by generating a

STOP condition, at which time the SMS8198 begins the

internal write cycle.

While the internal write cycle is in progress, the SMS8198

inputs are disabled, and the device will not respond to any

requests from the master. Refer to Figure 6 for the

address, ACKnowledge and data transfer sequence.

Page WRITE

The SMS8198 is capable of a 16-byte page write opera-

tion. It is initiated in the same manner as the byte-write

operation, but instead of terminating the write cycle after

the first data word, the master can transmit up to 15 more

words of data. After the receipt of each word, the

SMS8198 will respond with an ACKnowledge.

The SMS8198 automatically increments the address for

subsequent data words. After the receipt of each word,

the four low order address bits are internally incremented

by one. The high order five bits of the address byte remain

constant. Should the master transmit more than sixteen

words, prior to generating the STOP condition, the ad-

dress counter will “roll over,” and the previously written

data will be overwritten. As with the byte-write operation,

all inputs are disabled during the internal write cycle.

Refer to Figure 6 for the address, ACKnowledge and data

transfer sequence.

Acknowledges Transmitted from

SMS8198 to Master Receiver

If single byte-write only,

Stop bit issued here.

Acknowledges Transmitted from

SMS8198 to Master Receiver

SDA

Bus

Activity

A

A

A A A R C Word Address C

10 9 8 W K

K

Data Byte n

A

A

C Data Byte n+1 C

K

K

1010

0

AAAAAAAA

76543210

DDDDDDDD

76543210

DDDDDDDD

76543210

S

T

A

Device

Type

A10,A9,A8

R

T

Address Read/Write

0= Write

A

Data Byte n+15 C

K

DDDDDDDD

76543210

S

T

O

P

Slave Address

Master Sends Read

Request to Slave

Master Writes Word

Address to Slave

Master Writes

Data to Slave

Master Writes

Data to Slave

Master Writes

Data to Slave

Master Transmitter

to

Slave Receiver

Master Transmitter

to

Slave Receiver

Master Transmitter

to

Slave Receiver

Master Transmitter

to

Slave Receiver

Master Transmitter

to

Slave Receiver

Slave Transmitter

to

Master Receiver

Slave Transmitter

to

Master Receiver

Slave Transmitter

to

Master Receiver

Slave Transmitter

to

Master Receiver

Slave Transmitter

to

Master Receiver

Shading Denotes

SMS8198

SDA Output Active

2036 ILL8.0

Figure 6. Page/Byte WRITE Mode

2036 5.0 4/18/00

7

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