MC14046BCL データシートの表示（PDF） - Motorola => Freescale
部品番号
コンポーネント説明
メーカー
MC14046BCL Datasheet PDF : 7 Pages
| |||
Input Stage
XX
PCAin PCBin
PC1out
Input Stage
XX
PCAin PCBin
PHASE COMPARATOR 1
00
11
0
PHASE COMPARATOR 2
01
10
1
00
01
10
11
00
10
01
11
00
01
10
11
PC2out
0
3–State
Output Disconnected
1
LD
(Lock Detect)
0
1
0
Refer to Waveforms in Figure 3.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Figure 1. Phase Comparators State Diagrams
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Characteristic
Using Phase Comparator 1
Using Phase Comparator 2
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ No signal on input PCAin.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Phase angle between PCAin and PCBin.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Locks on harmonics of center frequency.
VCO in PLL system adjusts to center
frequency (f0).
VCO in PLL system adjusts to minimum
frequency (fmin).
90° at center frequency (f0), approaching 0_ Always 0_ in lock (positive rising edges).
and 180° at ends of lock range (2fL)
Yes
No
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Signal input noise rejection.
High
Low
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Lock frequency range (2fL).
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Capture frequency range (2fC).
The frequency range of the input signal on which the loop will stay locked if it was
initially in lock; 2fL = full VCO frequency range = fmax – fmin.
The frequency range of the input signal on which the loop will lock if it was initially
out of lock.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v Depends on low–pass filter characteristics
(see Figure 3). fC fL
fC = fL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Center frequency (f0).
The frequency of VCOout, when VCOin = 1/2 VDD
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VCO output frequency (f).
1
fmin =
R2(C1 + 32 pF)
(VCO input = VSS)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Note: These equations are intended to be
a design guide. Since calculated component
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ values may be in error by as much as a
factor of 4, laboratory experimentation may
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ be required for fixed designs. Part to part
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ frequency variation with identical passive
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ components is typically less than ± 20%.
1
fmax =
+ fmin
R1(C1 + 32 pF)
v v Where: 10K R1 1 M
v v 10K R2 1 M
v v 100pF C1 .01 µF
(VCO input = VDD)
Figure 2. Design Information
MC14046B
4
MOTOROLA CMOS LOGIC DATA
Share Link: 