ICS525-02(2000) データシートの表示（PDF） - Integrated Circuit Systems
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ICS525-02 Datasheet PDF : 8 Pages
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ICS525-01/02
OSCaR™ User Configurable Clock
Electrical Specifications (cont.)
Parameter
Conditions
AC CHARACTERISTICS (VDD = 3.3 V unless otherwise noted)
Input Frequency, crystal input
Input Frequency, clock input
Output Frequency, VDD = 4.5 to 5.5V
0 °C to 70 °C
ICS525-01, note 1
-40 °C to +85 °C
Output Frequency, VDD = 3.0 to 3.6V
0 °C to 70 °C
ICS525-01, note 1
-40 °C to +85 °C
Output Frequency, VDD = 4.5 to 5.5V
ICS525-02, note 1
-40 °C to +85 °C
Output Frequency, VDD = 3.0 to 3.6V
ICS525-02, note 1
-40 °C to +85 °C
Output Clock Rise Time
0.8 to 2.0V
Output Clock Fall Time
2.0 to 0.8V
Output Clock Duty Cycle, OD = 2, 4, 6, 8, or 10 at VDD/2
Output Clock Duty Cycle, OD = 3, 5, 7, or 9
at VDD/2
Output Clock Duty Cycle, OD = 1 (-02 only)
at VDD/2
Power Down Time, PD low to clocks stopped
Power Up Time, PD high to clocks stable
Absolute Clock Period Jitter, ICS525-01, Note 2 Deviation from mean
One Sigma Clock Period Jitter, ICS525-01, Note 2 One Sigma
Absolute Clock Period Jitter, ICS525-02, Note 2 Deviation from mean
One Sigma Clock Period Jitter, ICS525-02, Note 2 One Sigma
Minimum Typical Maximum Units
5
27
MHz
0.5
50
MHz
1
160
1
140
MHz
1
100
1
90
MHz
1.5
250
MHz
1
200
MHz
1
ns
1
ns
45
49 to 51
55
%
40
60
%
35
65
50
ns
10
ms
±140
ps
45
ps
±85
ps
30
ps
Note 1: The phase relationship between input and output can change at power up. For a fixed phase
relationship see the ICS527.
Note 2: For 16 MHz input, 100 MHz output. Use the -02 for lowest jitter.
MDS 525-01/02 I
7
Revision 071100
Printed 11/13/00
Integrated Circuit Systems, Inc. • 525 Race Street •San Jose• CA • 95126•(408) 295-9800tel• www.icst.com
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