
Vitesse Semiconductor
GENERAL DESCRIPTION:
The VersaCAT family adapts Ethernet technoloty to the WAN by efficiently provisioning Ethernet services across existing transport infrastructures while optimizing bandwidth utilization using hitless rate adaptation. It includes a suite of 2.5G and 10G mappers (HOVCAT, HOVCATe,LOVCAT) and multi-protocol WAN MACs
(Meigs-IIE, Campbell-I, and Barrington) that support Virtual Concatenation, fully integrated LCAS and GFP, as well as provides extensive Layer 2 aggregation, encapsulation and management features.
SPECIFICATIONS:
128 Virtual Concatenation Groups (VCGs) of STS-1/VC-3, STS-3C/VC-4, VT1.5/VT2.0, and TU-12/TU-11
High Order Path Overhead (POH) Ports for External Sourcing or Processing
System Packet Interface Level 4, Phase 2, 16-bit (SPI-4.2)
System Packet Interface Level 3, 32-bit (SPI-3)
72-bit External DDR SDRAM Interface
Dual-rate STS-48/STM-16 (TFI-5) or STS-12/STM-4 working & Protection Backplane Interfaces
Power Dissipation: 9W (LOVCAT192) 7W (LOVCAT48)
1760 HFCBGA Package