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NB6L239(2004) Hoja de datos - ON Semiconductor

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NB6L239

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  2013   lastest PDF  

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12 Pages

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80.3 kB

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ON-Semiconductor
ON Semiconductor 

Features
The NB6L239 is a high−speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; ÷1/2/4/8 and ÷2/4/8/16. Both divider circuits drive a pair of differential LVPECL outputs. (More device information on page 7).

• Maximum Clock Input Frequency, 3.0 GHz
• Input Compatibility with LVDS/LVPECL/CML/HSTL
• Rise/Fall Time 70 ps Typical
• < 10 ps Typical Output−to−Output Skew
• Ex. 622 MHz Input Generates 38.8 MHz to 622 MHz Outputs
• Internal 50 Ω Termination Provided
• Random Clock Jitter < 1 ps RMS
• Divide−by−1 Edge of QA Aligned to QB Divided Output
• Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
• Master Reset for Synchronization of Multiple Chips
• VBBAC Reference Output
• Synchronous Output Enable/Disable

Page Link's: 1  2  3  4  5  6  7  8  9  10  More Pages 

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Fabricante
2.5 V/3.3 V 2:1:15 Differential ECL/PECL ÷1/÷2 Clock Driver ( Rev : 2015 )
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2.5 V/3.3 V 1:15 Differential ECL/PECL ÷1/÷2 Clock Driver
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2.5 V/3.3 V 3.0 GHz Differential 1:4 LVPECL Fanout Buffer ( Rev : 2007 )
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2.5 V/3.3 V 3.0 GHz Differential 1:4 LVPECL Fanout Buffer ( Rev : 2012 )
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4:1 OR 2:1 DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
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4:1 OR 2:1 DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER ( Rev : 2001 )
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2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator
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3.3 V/5.0 VECL 1:15 Differential ÷1/÷2 Clock Driver
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3.3 V ECL 1:4 ÷1/÷2 Clock Fanout Buffer ( Rev : 2016 )
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