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MT28C3214P2FL-10TFL Hoja de datos - Micron Technology

MT28C3214P2FL image

Número de pieza
MT28C3214P2FL-10TFL

componentes Descripción

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page
42 Pages

File Size
384.7 kB

Fabricante
Micron
Micron Technology 

GENERAL DESCRIPTION
The MT28C3214P2FL and MT28C3214P2NFL combination Flash and SRAM memory devices provide a compact, low-power solution for systems where PCB real estate is at a premium. The dual-bank Flash is a high-performance, high-density, nonvolatile memory device with a revolutionary architecture that can significantly improve system performance.


FEATURES
• Flexible dual-bank architecture
• Support for true concurrent operations with no latency:
   Read bank b during program bank a and vice versa
   Read bank b during erase bank a and vice versa
• Organization: 2,048K x 16 (Flash)
   256K x 16 (SRAM)
• Basic configuration:
   Flash
      Bank a (4Mb Flash for data storage)
      – Eight 4K-word parameter blocks
      – Seven 32K-word blocks
      Bank b (28Mb Flash for program storage)
      – Fifty-six 32K-word main blocks
   SRAM
      4Mb SRAM for data storage
      – 256K-words
• F_VCC, VCCQ, F_VPP, S_VCC voltages1
   1.65V (MIN)/1.95V (MAX) F_VCC read voltage or
      1.80V (MIN)/2.20V (MAX) F_VCC read voltage
   1.65V (MIN)/1.95V (MAX) S_VCC read voltage or
      1.80V (MIN)/2.20V (MAX) S_VCC read voltage
   1.65V (MIN)/1.95V (MAX) VCCQ or
      1.80V (MIN)/2.20V (MAX) VCCQ
   1.80V (TYP) F_VPP (in-system PROGRAM/ERASE)
   0.0V (MIN)/2.20V (MAX) F_VPP (in-system
      PROGRAM/ERASE)2
   12V ±5% (HV) F_VPP (production programming
      compatibility)
• Asynchronous access time1
   Flash access time: 100ns or 110ns @ 1.65V F_VCC
   SRAM access time: 100ns @ 1.65V S_VCC
• Page Mode read access1
   Interpage read access: 100ns/110ns @ 1.65V F_VCC
   Intrapage read access: 35ns/45ns @ 1.65V F_VCC
• Low power consumption
• Enhanced suspend options
   ERASE-SUSPEND-to-READ within same bank
   PROGRAM-SUSPEND-to-READ within same bank
   ERASE-SUSPEND-to-PROGRAM within same bank
• Read/Write SRAM during program/erase of Flash
• Dual 64-bit chip protection registers for security
   purposes
• PROGRAM/ERASE cycles
   100,000 WRITE/ERASE cycles per block
• Cross-compatible command set support
   Extended command set
   Common flash interface (CFI) compliant

Page Link's: 1  2  3  4  5  6  7  8  9  10  More Pages 

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