DESCRIPTION
These circuits are high speed J–FET input single operational amplifiers incorporating well matched, high voltage J–FET and bipolar transistors in a monolithic integrated circuit.
The devices feature high slew rates, low input bias and offset currents, and low offset voltage temperature coefficient.

■ INTERNALLY ADJUSTABLE INPUT OFFSET VOLTAGE
■ LOW POWER CONSUMPTION
■ WIDE COMMON-MODE (UP TO VCC+) AND DIFFERENTIAL VOLTAGE RANGE
■ LOW INPUT BIAS AND OFFSET CURRENT
■ OUTPUT SHORT-CIRCUIT PROTECTION
■ HIGH INPUT IMPEDANCE J–FET INPUT STAGE
■ INTERNAL FREQUENCY COMPENSATION
■ LATCH UP FREE OPERATION
■ HIGH SLEW RATE : 16V/µs (typ)