GENERAL DESCRIPTION
The KA100O015E is a Multi Chip Package Memory which combines 4G bit NAND Flash Memory and 4G bit DDP synchronous high data rate Dynamic RAM.
NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 420μs(TBD) on the (2K+64)Word page and an erase operation can be performed in typical 3ms(TBD) on a (128K+4K)Word block. Data in the data register can be read out at 42ns cycle time per Word. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the writeintensive systems can take advantage of the device′s extended reliability of TBD program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The device is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.

In 4G bit DDP Mobile DDR, Synchronous design make a device controlled precisely with the use of system clock. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

The KA100O015E is suitable for use in data memory of mobile communication system to reduce not only mount area but also power consumption. This device is available in 137-ball FBGA Type.