Key Features
• VDD: 2.5V ± 0.2V, VDDQ: 2.5V ± 0.2V for DDR333, 400
• VDD: 2.5V ± 5%, VDDQ: 2.5V ± 5% for DDR500
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency : DDR333(2.5 Clock), DDR400(3 Clock), DDR500(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled atthe positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• Auto & Self refresh
• 15.6us refresh interval(4K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II Lead-Free and Halogen-Free package
• RoHS compliant