Functional Description
The CY7C1361C/CY7C1363C[1] is a 3.3V, 256K x 36/512K x 18 synchronous flow-through SRAMs, respectively designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

FEATUREs
■ Supports 100, 133 MHz Bus Operations
■ Supports 100 MHz Bus Operations (Automotive)
■ 256K × 36/512K × 18 Common I/O
■ 3.3V –5% and +10% Core Power Supply (VDD)
■ 2.5V or 3.3V I/O Power Supply (VDDQ)
■ Fast Clock-to-Output Times
    ❐ 6.5 ns (133-MHz version)
■ Provide High Performance 2-1-1-1 Access Rate
■ User-selectable Burst Counter supporting Intel® Pentium® Interleaved or Linear Burst Sequences
■ Separate Processor and Controller Address Strobes
■ Synchronous Self-timed Write
■ Asynchronous Output Enable
■ Available in Pb-free 100-Pin TQFP Package, Pb-free and non Pb-free 119-Ball BGA Package, and 165-Ball FBGA Package
■ TQFP Available with 3-Chip Enable and 2-Chip Enable
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ “ZZ” Sleep Mode option