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LTC2298C

Dual 14-Bit, 65/40/25Msps Low Power 3V ADCs

Linear Technology 

LTC2298/LTC2297/LTC2296

PI FU CTIO S

MUX (Pin 21): Digital Output Multiplexer Control. If MUX

isHigh,ChannelAcomesoutonDA0-DA13,OFA;Channel B

comes out on DB0-DB13, OFB. If MUX is Low, the output

busses are swapped and Channel A comes out on DB0-

DB13, OFB; Channel B comes out on DA0-DA13, OFA. To

multiplex both channels onto a single output bus, connect

MUX, CLKA and CLKB together.

SHDNB (Pin 22): Channel B Shutdown Mode Selection

Pin. Connecting SHDNB to GND and OEB to GND results

in normal operation with the outputs enabled. Connecting

SHDNB to GND and OEB to VDD results in normal opera-

tion with the outputs at high impedance. Connecting

SHDNB to VDD and OEB to GND results in nap mode with

the outputs at high impedance. Connecting SHDNB to VDD

and OEB to VDD results in sleep mode with the outputs at

high impedance.

OEB (Pin 23): Channel B Output Enable Pin. Refer to

SHDNB pin function.

DB0 – DB13 (Pins 24 to 30, 33 to 39): Channel B Digital

Outputs. DB13 is the MSB.

OGND (Pins 31, 50): Output Driver Ground.

OVDD (Pins 32, 49): Positive Supply for the Output Driv-

ers. Bypass to ground with 0.1µF ceramic chip capacitor.

OFB (Pin 40): Channel B Overflow/Underflow Output.

High when an overflow or underflow has occurred.

DA0 – DA13 (Pins 41 to 48, 51 to 56): Channel A Digital

Outputs. DA13 is the MSB.

OFA (Pin 57): Channel A Overflow/Underflow Output.

High when an overflow or underflow has occurred.

OEA (Pin 58): Channel A Output Enable Pin. Refer to

SHDNA pin function.

SHDNA (Pin 59): Channel A Shutdown Mode Selection

Pin. Connecting SHDNA to GND and OEA to GND results

in normal operation with the outputs enabled. Connecting

SHDNA to GND and OEA to VDD results in normal opera-

tion with the outputs at high impedance. Connecting

SHDNA to VDD and OEA to GND results in nap mode with

the outputs at high impedance. Connecting SHDNA to VDD

and OEA to VDD results in sleep mode with the outputs at

high impedance.

MODE (Pin 60): Output Format and Clock Duty Cycle

Stabilizer Selection Pin. Note that MODE controls both

channels. Connecting MODE to GND selects offset binary

output format and turns the clock duty cycle stabilizer off.

1/3 VDD selects offset binary output format and turns the

clock duty cycle stabilizer on. 2/3 VDD selects 2’s comple-

ment output format and turns the clock duty cycle stabi-

lizer on. VDD selects 2’s complement output format and

turns the clock duty cycle stabilizer off.

VCMA (Pin 61): Channel A 1.5V Output and Input Common

Mode Bias. Bypass to ground with 2.2µF ceramic chip

capacitor. Do not connect to VCMB.

SENSEA (Pin 62): Channel A Reference Programming Pin.

Connecting SENSEA to VCMA selects the internal reference

and a ±0.5V input range. VDD selects the internal reference

and a ±1V input range. An external reference greater than

0.5V and less than 1V applied to SENSEA selects an input

range of ±VSENSEA. ±1V is the largest valid input range.

GND (Exposed Pad) (Pin 65): ADC Power Ground. The

Exposed Pad on the bottom of the package needs to be

soldered to ground.

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