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LTC6994CS6-1

TimerBlox: Delay Block/Debouncer

Analog Devices 

LTC6994-1/LTC6994-2

OPERATION

The LTC6994 is built around a master oscillator with a 1µs

minimum period. The oscillator is controlled by the SET

pin current (ISET) and voltage (VSET), with a 1µs/50kΩ

conversion factor that is accurate to ±1.7% under typical

conditions.

tMASTER

=

1µs

50kΩ

•

VSET

ISET

A feedback loop maintains VSET at 1V ±30mV, leaving ISET

as the primary means of controlling the input-to-output

delay. The simplest way to generate ISET is to connect a

resistor (RSET) between SET and GND, such that ISET =

VSET/RSET . The master oscillator equation reduces to:

tMASTER

=

1µs

•

R SET

50kΩ

From this equation, it is clear that VSET drift will not affect

the input-to-output delay when using a single program

resistor (RSET). Error sources are limited to RSET toler-

ance and the inherent accuracy ∆tDELAY of the LTC6994.

RSET may range from 50k to 800k (equivalent to ISET

between 1.25µA and 20µA).

When the input makes a transition that will be delayed

(as determined by the part version and POL bit setting),

the master oscillator is enabled to time the delay. When

the desired duration is reached, the output is allowed to

transition.

The LTC6994 also includes a programmable frequency

divider which can further divide the frequency by 1, 8, 64,

512, 4096, 215, 218 or 221. This extends the delay duration

by those same factors. The divider ratio NDIV is set by a

resistor divider attached to the DIV pin.

tDELAY

=

NDIV

50kΩ

•

VSET

ISET

• 1µs

With RSET in place of VSET/ISET the equation reduces to:

tDELAY

=

NDIV • RSET

50kΩ

• 1µs

DIVCODE

The DIV pin connects to an internal, V+ referenced 4-bit A/D

converter that determines the DIVCODE value. DIVCODE

programs two settings on the LTC6994:

1. DIVCODE determines the frequency divider setting,

NDIV .

2. The DIVCODE MSB is the POL bit, and configures a

different polarity setting on the two versions.

a. LTC6994-1: POL selects rising or falling-edge delays.

POL = 0 will delay rising-edge transitions. POL = 1

will delay falling-edge transitions.

b. LTC6994-2: POL selects the output inversion.

POL = 1 inverts the output signal.

VDIV may be generated by a resistor divider between V+

and GND as shown in Figure 1.

2.25V TO 5.5V

V+

LTC6994

R1

DIV

R2

GND

699412 F01

Figure 1. Simple Technique for Setting DIVCODE

Table 1 offers recommended 1% resistor values that ac-

curately produce the correct voltage division as well as the

corresponding NDIV and POL values for the recommended

resistor pairs. Other values may be used as long as:

1. The VDIV/V+ ratio is accurate to ±1.5% (including resis-

tor tolerances and temperature effects)

2. The driving impedance (R1||R2) does not exceed 500kΩ.

Rev. C

12

For more information www.analog.com

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