WED9LAPC2C16V4BC Ver la hoja de datos (PDF) - White Electronic Designs => Micro Semi

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WED9LAPC2C16V4BC

512K x 32 SSRAM / 512K x 64 SDRAM

White Electronic Designs => Micro Semi 

WED9LAPC2C16V4BC

FIG. 15 SDRAM BURST READ SINGLE BIT WRITE CYCLE @ BURST LENGTH = 2

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14

15 16 17 18 19

GCLK

VCRAS

VCCAS

VCADDR

RAa

CAa RBb CAb

Note 2

RAc

CBc

CAd

VCBS

VCADDR9/AP

RAa

CL = 2

VCDATA

CL = 3

RBb

DAa0

DAa0

RAc

QAb0 QAb1

QAb0 QAb1

DBc0

DBc0

QAd0 QAd1

QAd0 QAd1

VCWE

VCDQM

Row Active

(A-Bank)

Row Active

(B-Bank)

Write

Read with

(A-Bank) Auto Precharge

(A-Bank)

Row Active

(A-Bank)

Read

(A-Bank)

Write with

Auto Precharge

(B-Bank)

Precharge

(Both Banks)

DON’T CARE

NOTES:

1. BRSW modes enabled by setting A9 “High” at MRS (Mode Register Set).

At the BRSW Mode, the burst length at Write is fixed to “1” regardless of programmed burst length.

2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle,

so in the case of BRSW write command, the next cycle starts the precharge.

July 2000 Rev. 0

21

White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com

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