CY8C5266AXI-LP132 Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza

componentes Descripción

fabricante

CY8C5266AXI-LP132

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor 

PSoC® 5LP: CY8C52LP Family

Datasheet

Figure 2-3. 68-pin QFN Part Pinout[3]

(TRACEDATA2] , GPIO) P2[6] 1

(TRACEDATA3] , GPIO) P2[7] 2

(I2C0 : SCL, SIO) P12[4] 3

(I2C0 : SDA, SIO) P12[5] 4

VSSB 5

IND 6

VBOOST 7

VBAT 8

VSSD 9

XRES 10

( TMS, SWDIO, GPIO) P1[0] 11

( TCK, SWDCK, GPIO) P1[1] 12

(Configurable XRES, GPIO) P1[2] 13

( TDO, SWV, GPIO) P1[3] 14

(TDI, GPIO) P1[4] 15

( NTRST, GPIO) P1[5] 16

VDDIO1 17

Lines show VDDIO

to I/O supply

association

QFN

(TOP VIEW)

51 P 0[ 3 ] (GPIO,EXTREF0)

50 P0[2] ( GPIO)

49 P0[1] ( GPIO)

48 P0[0] ( GPIO)

47 P12[3] (SIO)

46 P12[2] (SIO)

45 VSSD

44 VDDA

43 VSSA

42 VCCA

41 P15[3] ( GPIO, KHZ XTAL: XI)

40 P15[2] ( GPIO, KHZ XTAL:XO)

39 P12[1] (SIO, I2C1 : SDA)

38 P12[0] (SIO, 12C1 : SCL)

37 P3[7] ( GPIO)

36 P3[6] ( GPIO)

35 VDDIO3

Notes

3. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to

ground, it should be electrically floated and not connected to any other signal. For more information, see AN72845, Design Guidelines for QFN Devices.

4. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.

Document Number: 001-84933 Rev. *L

Page 7 of 114

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