IS61LPS51218J-225B Ver la hoja de datos (PDF) - Integrated Silicon Solution

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IS61LPS51218J-225B

256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINED, SINGLE-CYCLE DESELECT STATIC RAM

Integrated Silicon Solution 

IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J

®

ISSI

TEST DATA OUT (TDO)

The TDO output pin is used to serially clock data-out from

the registers. The output is active depending on the

current state of the TAP state machine (see TAP Controller

State Diagram). The output changes on the falling edge of

TCK and TDO is connected to the Least Significant Bit

(LSB) of any register.

PERFORMING A TAP RESET

A Reset is performed by forcing TMS HIGH (VCC) for five

rising edges of TCK. RESET may be performed while the

SRAM is operating and does not affect its operation. At

power-up, the TAP is internally reset to ensure that TDO

comes up in a high-Z state.

TAP REGISTERS

Registers are connected between the TDI and TDO pins

and allow data to be scanned into and out of the SRAM test

circuitry. Only one register can be selected at a time

through the instruction registers. Data is serially loaded

into the TDI pin on the rising edge of TCK and output on the

TDO pin on the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the

instruction register. This register is loaded when it is

placed between the TDI and TDO pins. (See TAP Controller

Block Diagram) At power-up, the instruction register is

loaded with the IDCODE instruction. It is also loaded with

the IDCODE instruction if the controller is placed in a reset

state as previously described.

When the TAP controller is in the CaptureIR state, the two

least significant bits are loaded with a binary “01” pattern

to allow for fault isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers,

it is sometimes advantageous to skip certain states. The

bypass register is a single-bit register that can be placed

between TDI and TDO pins. This allows data to be shifted

through the SRAM with minimal delay. The bypass register

is set LOW (GND) when the BYPASS instruction is

executed.

Boundary Scan Register

The boundary scan register is connected to all input and

output pins on the SRAM. Several no connect (NC) pins are

also included in the scan register to reserve pins for higher

density devices. The x36 configuration has a 70-bit-long

register and the x18 configuration has a 51-bit-long

register. The boundary scan register is loaded with the

contents of the RAM Input and Output ring when the TAP

controller is in the Capture-DR state and then placed

between the TDI and TDO pins when the controller is moved

to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD

and SAMPLE Z instructions can be used to capture the

contents of the Input and Output ring.

The Boundary Scan Order tables show the order in which

the bits are connected. Each bit corresponds to one of the

bumps on the SRAM package. The MSB of the register is

connected to TDI, and the LSB is connected to TDO.

Scan Register Sizes

Register Name

Instruction

Bypass

ID

Boundary Scan

Bit Size (x18)

3

1

32

51

Bit Size (x36)

3

1

32

70

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit

code during the Capture-DR state when the IDCODE

command is loaded to the instruction register. The IDCODE

is hardwired into the SRAM and can be shifted out when

the TAP controller is in the Shift-DR state. The ID register

has vendor code and other information described in the

Identification Register Definitions table.

TAP INSTRUCTION SET

Eight instructions are possible with the three-bit instruction

register and all combinations are listed in the Instruction

Code table. Three instructions are listed as RESERVED

and should not be used and the other five instructions are

described below. The TAP controller used in this SRAM is

not fully compliant with the 1149.1 convention because

some mandatory instructions are not fully implemented.

The TAP controller cannot be used to load address, data or

control signals and cannot preload the Input or Output

buffers. The SRAM does not implement the 1149.1 com-

mands EXTEST or INTEST or the PRELOAD portion of SAMPLE/

PRELOAD; instead it performs a capture of the Inputs and Output

ring when these instructions are executed. Instructions are

loaded into the TAP controller during the Shift-IR state when

the instruction register is placed between TDI and TDO.

During this state, instructions are shifted from the instruc-

tion register through the TDI and TDO pins. To execute an

instruction once it is shifted in, the TAP controller must be

moved into the Update-IR state.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

21

PRELIMINARYINFORMATION Rev. 00B

04/29/02

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