DS2181A Ver la hoja de datos (PDF) - Maxim Integrated

Número de pieza

componentes Descripción

fabricante

DS2181A

CEPT Primary Rate Transceiver

Maxim Integrated 

RECEIVE SIGNALING Table 7

FRAME # RSD1 VALID DURING

TIMESLOT #

0

15, -2

1

-2, 17

2

1, 18

3

2, 19

4

3, 20

5

4, 21

6

5, 22

7

6, 23

8

7, 24

9

8, 25

10

9, 26

11

10, 27

12

11, 28

13

12, 29

14

13, 30

15

14, 31

DS2181A

NOTES: (Applicable only to CAS systems)

1. RSD is valid for the least significant nibble in each indicated timeslot. Timeslot A data appears in bit

5, B in bit 6, C in bit 7 and D in bit 8.

2. RSD does not output valid data during timeslots 0 and 16.

RECEIVE MULTIFRAME TIMING Figure 15

RECEIVE TIMING

The receive side output timing set is identical to that found on the transmit side. The user can tie receive

outputs directly to the transmit inputs for drop and insert applications. The received data of RPOS, RNEG

appear at RSER after six RCLK delays, without any change except for the HDB3-to-NRZ conversion

when HDB3 is enabled.

17 of 32

Share Link: