ADSP-21367 Ver la hoja de datos (PDF) - Analog Devices

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fabricante

ADSP-21367

SHARC Processors

Analog Devices 

SDRAM Interface Enable/Disable Timing (166 MHz SDCLK)

Table 24. SDRAM Interface Enable/Disable Timing1

Parameter

Switching Characteristics

tDSDC

tENSDC

tDSDCC

tENSDCC

tDSDCA

tENSDCA

Command Disable After CLKIN Rise

Command Enable After CLKIN Rise

SDCLK Disable After CLKIN Rise

SDCLK Enable After CLKIN Rise

Address Disable After CLKIN Rise

Address Enable After CLKIN Rise

1 For fCCLK = 400 MHz (SDCLK ratio = 1:2.5).

ADSP-21367/ADSP-21368/ADSP-21369

Min

4.0

3.8

2 × tPCLK – 4

Max

2 × tPCLK + 3

8.5

9.2

4 × tPCLK

Unit

ns

ns

ns

ns

ns

ns

CLKIN

COMMAND

SDCLK

ADDR

COMMAND

SDCLK

ADDR

tDSDC

tDSDCC

tDSDCA

tENSDC

tENSDCC

tENSDCA

Figure 17. SDRAM Interface Enable/Disable Timing

Rev. C | Page 27 of 56 | January 2008

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