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ADT7301ARTZ-REEL Ver la hoja de datos (PDF) - Analog Devices

Número de pieza
componentes Descripción
fabricante
ADT7301ARTZ-REEL Datasheet PDF : 14 Pages
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ADT7301
Preliminary Technical Data
TIMING CHARACTERISTICS
Guaranteed by design and characterization, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD)
and timed from a voltage level of 1.6 V.
TA = TMIN to TMAX, VDD = 2.7 V to 5.5 V, unless otherwise noted.
Table 2.
Parameter1
t1
t2
t3
t4 2
t5
t6
t7
t82
Limit
5
25
25
35
20
5
5
40
Unit
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns max
Comments
CS to SCLK Setup Time
SCLK High Pulse Width
SCLK Low Pulse Width
Data Access Time after SCLK Falling Edge
Data Setup Time prior to SCLK Rising Edge
Data Hold Time after SCLK Rising Edge
CS to SCLK Hold Time
CS to DOUT High Impedance
1 See Figure 13. for SPI Timing diagram.
2 Measured with the load circuit of Figure 2
200µA
IOL
TO
OUTPUT
PIN CL
50pF
1.6V
200µA
IOH
Figure 2. Load Circuit for Data Access Time and Bus Relinquish Time
Rev. PrJ | Page 4 of 14

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