AD7175-8BCPZ Ver la hoja de datos (PDF) - Analog Devices

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AD7175-8BCPZ

24-Bit, 8-/16-Channel, 250 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers

Analog Devices 

Data Sheet

AD7175-8

SPECIFICATIONS

AVDD1 = 4.5 V to 5.5 V, AVDD2 = 2 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS,

internal master clock (MCLK) = 16 MHz, TA = TMIN to TMAX (−40°C to +105°C), unless otherwise noted.

Table 1.

Parameter

ADC SPEED AND PERFORMANCE

Output Data Rate (ODR)

No Missing Codes1

Resolution

Noise

ACCURACY

Integral Nonlinearity (INL)

Offset Error2

Offset Drift

Gain Error2

Gain Drift1

REJECTION

Power Supply Rejection

Common-Mode Rejection

At DC

At 50 Hz, 60 Hz1

Normal Mode Rejection1

ANALOG INPUTS

Differential Input Range

Absolute Voltage Limits1

Input Buffers Disabled

Input Buffers Enabled

Analog Input Current

Input Buffers Disabled

Input Current

Input Current Drift

Input Buffers Enabled

Input Current

Input Current Drift

Crosstalk

INTERNAL REFERENCE

Output Voltage

Initial Accuracy3

Temperature Coefficient1

0°C to 105°C

−40°C to +105°C

Reference Load Current, ILOAD

Power Supply Rejection

Load Regulation

Voltage Noise

Voltage Noise Density

Test Conditions/Comments

Min

Typ

5

Excluding sinc3 filter ≥ 125 kSPS

24

See Table 19 to Table 23

See Table 19 to Table 23

All input buffers enabled

All input buffers disabled

Internal short

Internal short

±4.5

±1

±60

±150

±80

±0.5

AVDD1, AVDD2, for VIN = 1 V

VIN = 0.1 V

90

95

20 Hz output data rate (post filter), 50 Hz ± 120

1 Hz and 60 Hz ± 1 Hz

50 Hz ± 1 Hz and 60 Hz ± 1 Hz

Internal clock, 20 SPS ODR (postfilter)

71

90

External clock, 20 SPS ODR (postfilter)

85

90

VREF = (REF+) − (REF−)

±VREF

AVSS − 0.05

AVSS

Max

Unit

250,000

SPS

Bits

10

±4.5

±110

±0.75

ppm of FSR

ppm of FSR

µV

nV/°C

ppm of FSR

ppm/°C

dB

dB

dB

dB

dB

V

AVDD1 + 0.05 V

AVDD1

V

External clock

Internal clock

AVDD1 − 0.2 V to AVSS + 0.2 V

AVDD1 to AVSS

1 kHz input

100 nF external capacitor to AVSS

REFOUT, with respect to AVSS

REFOUT, TA = 25°C

AVDD1, AVDD2 (line regulation)

∆VOUT/∆ILOAD

eN, 0.1 Hz to 10 Hz, 2.5 V reference

eN, 1 kHz, 2.5 V reference

−0.12

−10

±48

±0.75

±4

±30

±75

±1

−120

2.5

±2

±3

95

32

4.5

215

+0.12

±5

±10

+10

µA/V

nA/V/°C

nA/V/°C

nA

pA/°C

nA/°C

dB

V

% of V

ppm/°C

ppm/°C

mA

dB

ppm/mA

µV rms

nV/√Hz

Rev. 0 | Page 3 of 64

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