Preliminary Technical Data
FUNCTIONAL BLOCK DIAGRAM
AD5750
CLEAR
CLRSEL
SCLK/OUTEN*
SDIN/R0*
SYNC/RSEL*
SDO/VFAULT*
HW SELECT
VIN
VREF
DVCC GND AVDD GND COMP1 COMP2
INPUT SHIFT
REGISTER
AND
CONTROL
LOGIC
STATUS REG
VOUT RANGE
SCALING
VSENSE+
VOUT
VOUT SHORT FAULT
VSENSE-
V DD
R2
R3
RESET
FAULT/TEMP*
NC/IFAULT*
IOUT RANGE
SCALING
OVERTEMP
VOUT SHORT FAULT
IOUT OPEN FAULT
OUTPUT RANGE ERROR
AD5750
POWER
ON
RESET
RSET
Vx
V SS
IOUT OPEN FAULT
REXT1
REXT2
IOUT
AD2/R1* AD1/R2* AD0/R3*
AVSS
Figure 1. Functional Block Diagram
* Denotes shared pin. Software mode denoted by regular text, hardware mode denoted by bold
text. E.G. for FAULT/TEMP pin, in software mode this pin will take on FAULT function. In
Hardware mode, this pin will take on TEMP function.
Rev. PrC | Page 3 of 25