PEB2047-N Ver la hoja de datos (PDF) - Infineon Technologies

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PEB2047-N

Memory Time Switch Large

Infineon Technologies 

PEB 2047

PEB 2047-16

Constant delay (D12 = 0): read output time-slot from data memory (not DMO)

Minimal delay (D12 = 1):

if number of input time-slot to be switched to current output ≤ IADP

then

read output time-slot from data memory DMI

else

read output time-slot from data memory (not DMI)

The synchronization of this procedure will be achieved by a rising edge of the synchron pulse SP,

which is always sampled with the falling edge of the device clock.

Different modes of operation are configurable at the PCM-input interface (see table 3).

Furthermore, 8 PCM-input lines can be aligned with individual clock shift values to compensate

different line delays. If more than 8 inputs are used one clock shift value controls up to two ports at

the same time.

The input lines IN8 to IN15 can be used as additional frame-measurement inputs (FS(0:7)). After

synchronizing the device by the SP pulse the FS inputs can be evaluated on a per port basis. This

evaluation procedure is started by a microprocessor command. As a result the input counter value

on the rising edge of the FS signal can be read from an internal register. Thus delay compensation

is easily managed by programming appropriate clock shift values and/or a possible software offset.

During operation of the chip a frame length check is also supplied, which controls correct

synchronization by the SP pulse and generates an interrupt in case of lost or achieved

synchronization.

The output buffer operation is controlled by mode selection and the chosen clock-rate (4096 kHz,

8192 kHz or 16 384 kHz) (see table 2). Shifting of the output frame is also possible, but all output-

lines are affected the same way.

The unused output ports are tristated by mode selection, whereas unused time-slots are tristated by

an additional bit in the control memory. By using this tristate capability the MTSL can be easily

expanded to a time switch of any size (see figure 2 to 5).

Semiconductor Group

13

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