HI5812 Ver la hoja de datos (PDF) - Renesas Electronics
Número de pieza
componentes Descripción
fabricante
HI5812
Renesas Electronics
HI5812 Datasheet PDF : 16 Pages
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HI5812
Absolute Maximum Ratings
Supply Voltage
VDD to VSS . . . . . . . . . . . . . . . . . . . . (VSS -0.5V) < VDD < +6.5V
VAA+ to VAA- . . . . . . . . . . . . . . . . . . . (VSS -0.5V) to (VSS +6.5V)
VAA+ to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
Analog and Reference Inputs
VIN, VREF+, VREF- . . . . . . . . (VSS -0.3V) < VINA < (VDD +0.3V)
Digital I/O Pins . . . . . . . . . . . . . . . (VSS -0.3V) < VI/O < (VDD +0.3V)
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Information
Thermal Resistance (Typical, Note 1)
JA (oC/W)
PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
Maximum Junction Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65C to 150oC
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER
ACCURACY
VDD = VAA+ = 5V, VREF+ = +4.608V, VSS = VAA- = VREF- = GND, CLK = External 750kHz,
Unless Otherwise Specified
25oC
-40oC TO 85oC
TEST CONDITIONS
MIN TYP MAX
MIN
MAX
UNITS
Resolution
12
-
-
12
-
Bits
Integral Linearity Error, INL
J
(End Point)
K
-
-
1.5
-
-
-
1.0
-
1.5
LSB
1.0
LSB
Differential Linearity Error, DNL
J
-
-
2.0
-
2.0
LSB
K
-
-
1.0
-
1.0
LSB
Gain Error, FSE
J
(Adjustable to Zero)
K
-
-
3.0
-
-
-
2.5
-
3.0
LSB
2.5
LSB
Offset Error, VOS
J
(Adjustable to Zero)
K
-
-
2.0
-
-
-
1.0
-
2.0
LSB
1.0
LSB
Power Supply Rejection, PSRR
Offset Error PSRR
Gain Error PSRR
DYNAMIC CHARACTERISTICS
VREF = 4V
VDD VAA+ = 5V 5%
VDD VAA+ = 5V 5%
-
-
±0.1 0.5
±0.1 0.5
0.5
LSB
0.5
LSB
Signal to Noise Ratio, SINAD
RMS Signal
RMS Noise + Distortion
Signal to Noise Ratio, SNR
RMS Signal
RMS Noise
Total Harmonic Distortion, THD
J fS = Internal Clock, fIN = 1kHz
-
68.8
-
-
fS = 750kHz, fIN = 1kHz
69.2
K fS = Internal Clock, fIN = 1kHz
-
71.0
-
-
fS = 750kHz, fIN = 1kHz
71.5
J fS = Internal Clock, fIN = 1kHz
-
70.5
-
-
fS = 750kHz, fIN = 1kHz
71.1
K fS = Internal Clock, fIN = 1kHz
-
71.5
-
-
fS = 750kHz, fIN = 1kHz
72.1
J fS = Internal Clock, fIN = 1kHz
-
-73.9
-
-
fS = 750kHz, fIN = 1kHz
-73.8
K fS = Internal Clock, fIN = 1kHz
-
-80.3
-
-
fS = 750kHz, fIN = 1kHz
-79.0
-
dB
dB
-
dB
dB
-
dB
dB
-
dB
dB
-
dBc
dBc
-
dBc
dBc
FN3214 Rev 6.00
March 31, 2005
Page 3 of 16
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