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CS51312

Synchronous CPU Buck Controller for 12 V Only Applications

ON Semiconductor 

CS51312

non−inverting input provides the hiccup timing for the

Overcurrent Protection, Soft Start function, and regulator

output enable.

VCC2 Charge Pump

In order to fully turn on the high side NFET, a voltage

greater than the input voltage must be applied to VCC2 to bias

the GATE(H) driver. Referring to the application diagram on

page 2; a simple charge pump circuit can be implemented

for this purpose through capacitor C6, resistor R1, and

diodes D1 and D2. The input voltage, less the drop in D1 is

stored in C6 during the off−time period. When the high−side

FET turns on, it drives the inductor switching node and C6

high causing Schottky diode D1 to reverse bias. The charge

stored in C6 is transferred to VCC2 through R1. Zener diode

D2 clamps the VCC2 voltage to 18 V to prevent the VCC2

from exceeding its 20 V Max rating (see Figure 9).

Channel 1 − Charge Pump Switching Node (10 V/div)

Channel 2 − VCC2 (10 V/div)

Channel 3 − GATE(H) (10 V/div)

Channel 4 − Inductor Switching Node (10 V/div)

Figure 9. VCC2 Charge Pump Operation (1.0 ms/div)

Hysteresis of 300 mV (typ) is provided for noise immunity.

The Error Amp Capacitor connected to the COMP pin is

charged by a 30 μA current source. This capacitor must be

charged to 1.1 V (typ) so that it exceeds the PWM

comparator’s offset before the V2 PWM control loop

permits switching to occur.

When VCC1 has exceeded 8.4 V and COMP has charged

to 1.1 V, the upper Gate driver (GATE(H)) is activated,

turning on the upper FET. This causes current to flow

through the output inductor and into the output capacitors

and load according to the following equation:

I + (VIN * VOUT)

T

L

GATE(H) and the upper NFET remain on and inductor

current ramps up until the initial pulse is terminated by either

the PWM control loop or the overcurrent protection. This

initial surge of in−rush current minimizes startup time, but

avoids overstressing of the regulator’s power components.

The PWM comparator will terminate the initial pulse if

the regulator output exceeds the voltage on the COMP pin

plus the 1.1 V PWM comparator offset prior to the drop

across the current sense resistor exceeding the current limit

threshold. In this case, the PWM control loop has achieved

regulation and the initial pulse is then followed by a constant

off time as programmed by the COFF capacitor. The COMP

capacitor will continue to slowly charge and the regulator

output voltage will follow it, less the 1.1 V PWM offset, until

it achieves the voltage programmed by the DAC’s VID

input. The Error Amp will then source or sink current to the

COMP cap as required to maintain the correct regulator DC

output voltage. Since the rate of increase of the COMP pin

voltage is typically set much slower than the regulator’s slew

capability, inrush current, output voltage, and duty cycle all

gradually increase from zero. (See Figures 10 and 11).

Startup

The CS51312 provides a controlled startup of regulator

output voltage and features Programmable Soft Start

implemented through the Error Amp and external

Compensation Capacitor. This feature, combined with

overcurrent protection, prevents stress to the regulator

power components and overshoot of the output voltage

during startup.

As Power is applied to the regulator, the CS51312

Undervoltage Lockout circuit (UVL) monitors the ICs

supply voltage (VCC1) which is typically connected to the

+12 V input. The UVL circuit prevents the NFET gates from

being activated until VCC1 exceeds the 8.4 V (typ) threshold.

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