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MAX3671ETN

Low-Jitter Frequency Synthesizer with Selectable Input Reference

Microsemi Corporation 

Low-Jitter Frequency Synthesizer

with Selectable Input Reference

Master Reset

After power-up, an external master reset (MR) can be

provided to reset the internal dividers. This input

requires a minimum reset pulse width of 100ns (active

low) and is asynchronous to the reference clock. While

MR is low, all clock outputs are held to logic-low (OUTxx

= low, OUTxx = high). See Table 6 for the output signal

status during master reset. When the master reset input

is deasserted (MR = 1), the PLL starts to lock to the ref-

erence clock selected by SEL_CLK.

Master reset is only needed for applications where

divider configurations are changed on the fly and the

clock outputs need to maintain phase alignment. A

master reset is not required at power-up.

External Feedback for Zero-Delay Buffer

The MAX3671 can be operated with either internal or

external PLL feedback path, controlled by the FB_SEL

input. Connecting FB_SEL to GND selects internal feed-

back. For applications where a known phase relation-

ship between the reference clock input and the external

feedback input (FB_IN, FB_IN) are needed for phase

synchronization, connect FB_SEL to VCC for zero-delay

buffer configuration and provide external feedback to

the FB_IN input.

PLL Bypass Mode

PLL bypass mode is provided for test purposes. In PLL

bypass mode (PLL_BYPASS = 1), the selected refer-

ence clock is connected to the LVPECL clock outputs

directly. The output clock frequency is the same as the

input clock frequency and the clock qualification func-

tion is not valid. To reduce spurious jitter in bypass

mode, the internal VCO should be disabled by shorting

the CREG pin to GND.

Applications Information

Interfacing with LVPECL Inputs

Figure 5 shows the equivalent LVPECL input circuit for

REFCLK0, REFCLK1, and FB_IN. These inputs are

internally biased to allow AC- or DC-coupling and have

> 40kΩ differential input impedance. When AC-cou-

pled, these inputs can accept LVDS, CML, and

LVPECL signals. Unused reference clock inputs should

be left open.

Interfacing with LVPECL Outputs

Figure 6 shows the equivalent LVPECL output circuit.

These outputs are designed to drive a pair of 50Ω

transmission lines terminated with 50Ω to VTT = VCC -

2V. If a separate termination voltage (VTT) is not avail-

able, other termination methods can be used such as

those shown in Figures 7 and 8. Unused outputs,

enabled or disabled, can be left open or properly termi-

nated. For more information on LVPECL terminations

and how to interface with other logic families, refer to

Application Note 291: HFAN-01.0: Introduction to LVDS,

PECL, and CML.

Layout Considerations

The clock inputs and outputs are critical paths for the

MAX3671, and care should be taken to minimize dis-

continuities on the transmission lines. Maintain 100Ω

differential (or 50Ω single-ended) impedance in and out

of the MAX3671. Avoid using vias and sharp corners.

Termination networks should be placed as close as

possible to receiving clock inputs. Provide space

between differential output pairs to reduce crosstalk,

especially if the A and B group outputs are operating at

different frequencies.

Table 6. Output Signal Status During Power-On-Reset or Master Reset

OUTPUT

IN0FAIL

IN1FAIL

LOCK

OUTA[3:0]

OUTB[4:0]

DURING POWER-ON-RESET

(FOR ~ 20μs AFTER VCC > 3.0V)

DURING MASTER RESET

(MR = 0)

1

1

1

Logic-Low

Logic-Low

NOTES

Forced high regardless of reference

input qualification.

Forced high regardless of reference

input qualification.

PLL out-of-lock.

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