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FW802A-DB

Low-Power PHY IEEE* 1394A-2000 Two-Cable Transceiver/Arbiter Device

Agere -> LSI Corporation 

Data Sheet, Rev. 3

June 2001

FW802A Low-Power PHY IEEE

Two-Cable Transceiver/Arbiter Device

Internal Register Configuration (continued)

The meaning of the register fields with the port status page are defined by Table 11 below.

Table 11. PHY Register Port Status Page Fields

Field

AStat

Size Type

2

r

BStat

Child

2

r

1

r

Connected

1

r

Bias

1

r

Disabled

1 rw

Negotiated_speed 3

r

Int_enable

1 rw

Fault

1 rw

Power Reset

Value

—

—

0

0

0

0

000

0

0

Description

TPA line state for the port:

002 = invalid

012 = 1

102 = 0

112 = Z

TPB line state for the port (same encoding as AStat).

If equal to one, the port is a child; otherwise, a parent. The

meaning of this bit is undefined from the time a bus reset is

detected until the PHY transitions to state T1: Child Hand-

shake during the tree identify process (see Section 4.4.2.2 in

IEEE Standard 1394-1995).

If equal to one, the port is connected.

If equal to one, incoming TPBIAS is detected.

If equal to one, the port is disabled.

Indicates the maximum speed negotiated between this PHY

port and its immediately connected port; the encoding is the

same as for they PHY register Max_speed field.

Enable port event interrupts. When set to one, the PHY will

set Port_event to one if any of connected, bias, disabled, or

fault (for this port) change state.

Set to one if an error is detected during a suspend or resume

operation. A write of one to this bit clears it to zero.

Agere Systems Inc.

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