MC100LVEL12DTG(2008) Ver la hoja de datos (PDF) - ON Semiconductor
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MC100LVEL12DTG Datasheet PDF : 8 Pages
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Qa 1
Qb 2
Qa 3
Qb 4
MC100LVEL12
8 VCC
7 D0
6 D1
5 VEE
Table 1. PIN DESCRIPTION
PIN
D0, D1
Qa, Qa; Qb, Qb
VCC
VEE
EP
FUNCTION
ECL Data Inputs
ECL Data Outputs
Positive Supply
Negative Supply
(DFN8 only) Thermal exposed pad
must be connected to a sufficient
thermal conduit. Electrically connect
to the most negative supply (GND)
or leave unconnected, floating open.
Figure 1. Logic Diagram and Pinout Assignment
Table 2. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE
NECL Mode Power Supply
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
Iout
Output Current
VEE = 0 V
VCC = 0 V
VEE = 0 V
VCC = 0 V
Continuous
Surge
VI VCC
VI VEE
8 to 0
V
−8 to 0
V
6 to 0
V
−6 to 0
V
50
mA
100
mA
TA
Operating Temperature Range
Tstg
Storage Temperature Range
qJA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
8 SOIC
8 SOIC
−40 to +85
−65 to +150
190
130
°C
°C
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
8 SOIC
qJA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
8 TSSOP
8 TSSOP
41 to 44 ± 5%
185
140
°C/W
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
8 TSSOP
qJA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
DFN8
DFN8
41 to 44 ± 5%
129
84
°C/W
°C/W
°C/W
Tsol
Wave Solder
Pb <2 to 3 sec @ 248°C
Pb−Free <2 to 3 sec @ 260°C
265
°C
265
qJC
Thermal Resistance (Junction−to−Case)
(Note 1)
DFN8
35 to 40
°C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
http://onsemi.com
2
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