Nexperia
74LVC1G02
Single 2-input NOR gate
14. Abbreviations
Table 11. Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 12. Revision history
Document ID
Release date Data sheet status
Change notice Supersedes
74LVC1G02 v.12
Modifications:
20161129
Product data sheet
-
74LVC1G02 v.11
• Table 7: The maximum limits for leakage current and supply current have changed.
74LVC1G02 v.11
Modifications:
20120629
Product data sheet
-
• Added type number 74LVC1G02GX (SOT1226)
74LVC1G02 v.10
74LVC1G02 v.10
Modifications:
20120305
Product data sheet
-
• Package outline drawing of SOT886 (Figure 12) modified.
74LVC1G02 v.9
74LVC1G02 v.9
Modifications:
20111209
Product data sheet
-
• Legal pages updated.
74LVC1G02 v.8
74LVC1G02 v.8
20101020
Product data sheet
-
74LVC1G02 v.7
74LVC1G02 v.7
20070718
Product data sheet
-
74LVC1G02 v.6
74LVC1G02 v.6
20060914
Product data sheet
-
74LVC1G02 v.5
74LVC1G02 v.5
20040907
Product specification
-
74LVC1G02 v.4
74LVC1G02 v.4
20021002
Product specification
-
74LVC1G02 v.3
74LVC1G02 v.3
20020515
Product specification
-
74LVC1G02 v.2
74LVC1G02 v.2
20010411
Product specification
-
74LVC1G02 v.1
74LVC1G02 v.1
20001114
Product specification
-
-
74LVC1G02
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 29 November 2016
© Nexperia B.V. 2017. All rights reserved
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