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CS5166

5−Bit Synchronous CPU Controller with Power Good and Current Limit

ON Semiconductor 

CS5166

APPLICATIONS INFORMATION

THEORY OF OPERATION

V2 Control Method

The V2 method of control uses a ramp signal that is

generated by the ESR of the output capacitors. This ramp is

proportional to the AC current through the main inductor

and is offset by the value of the DC output voltage. This

control scheme inherently compensates for variation in

either line or load conditions, since the ramp signal is

generated from the output voltage itself. This control

scheme differs from traditional techniques such as voltage

mode, which generates an artificial ramp, and current mode,

which generates a ramp from inductor current.

since the error amplifier bandwidth can be rolled off at a low

frequency. Enhanced noise immunity improves remote

sensing of the output voltage, since the noise associated with

long feedback traces can be effectively filtered.

The Bode plot in Figure 10 shows the gain and phase

margin of the CS5166 single pole feedback loop and

demonstrates the overall stability of the CS5166−based

regulator.

PWM

Comparator

+

GATE(H)

C

−

GATE(L)

Ramp

Signal

VFB

COMP

Error

Signal

Error

Amplifier −

E

+

Reference

Voltage

Figure 9. V2 Control Diagram

The V2 control method is illustrated in Figure 9. The

output voltage is used to generate both the error signal and

the ramp signal. Since the ramp signal is simply the output

voltage, it is affected by any change in the output regardless

of the origin of that change. The ramp signal also contains

the DC portion of the output voltage, which allows the

control circuit to drive the main switch to 0% or 100% duty

cycle as required.

A change in line voltage changes the current ramp in the

inductor, affecting the ramp signal, which causes the V2

control scheme to compensate the duty cycle. Since the

change in inductor current modifies the ramp signal, as in

current mode control, the V2 control scheme has the same

advantages in line transient response.

A change in load current will have an affect on the output

voltage, altering the ramp signal. A load step immediately

changes the state of the comparator output, which controls

the main switch. Load transient response is determined only

by the comparator response time and the transition speed of

the main switch. The reaction time to an output load step has

no relation to the crossover frequency of the error signal

loop, as in traditional control methods.

The error signal loop can have a low crossover frequency,

since transient response is handled by the ramp signal loop.

The main purpose of this ‘slow’ feedback loop is to provide

DC accuracy. Noise immunity is significantly improved,

Figure 10. Feedback Loop Bode Plot

Line and load regulation are drastically improved because

there are two independent voltage loops. A voltage mode

controller relies on a change in the error signal to

compensate for a deviation in either line or load voltage.

This change in the error signal causes the output voltage to

change corresponding to the gain of the error amplifier,

which is normally specified as line and load regulation.

A current mode controller maintains fixed error signal

under deviation in the line voltage, since the slope of the

ramp signal changes, but still relies on a change in the error

signal for a deviation in load. The V2 method of control

maintains a fixed error signal for both line and load

variation, since the ramp signal is affected by both line and

load.

Constant Off Time

To maximize transient response, the CS5166 uses a

constant off time method to control the rate of output pulses.

During normal operation, the off time of the high side switch

is terminated after a fixed period, set by the COFF capacitor.

To maintain regulation, the V2 control loop varies switch on

time. The PWM comparator monitors the output voltage

ramp, and terminates the switch on time.

Constant off time provides a number of advantages.

Switch duty cycle can be adjusted from 0 to 100% on a pulse

by pulse basis when responding to transient conditions. Both

0% and 100% duty cycle operation can be maintained for

extended periods of time in response to load or line

transients. PWM slope compensation to avoid

sub−harmonic oscillations at high duty cycles is avoided.

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