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74ALVC16834ADGG Datasheet PDF : 15 Pages
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Nexperia
74ALVC16834A
18-bit registered driver with inverted register enable; 3-state
An
input
LE
input
VM
tsu
th
VM
VM
tsu
VI
GND
th
VI
VM
GND
002aac728
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
Figure 7. Data set-up and hold times, An input to LE
input
CP
input
An
input
VM
tsu th
tsu th
VI
GND
VI
GND
Yn
output
VOH
VOL
002aac730
Measurement points are given in Table 8.
VOL and VOH are typical voltage output drop that occur with
the output load.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
Figure 9. Data set-up and hold times, An input to CP
input
CP input
Yn output
1 / fmax
VM
tw
tPHL
VM
VM
tPLH
VI
GND
VOH
VOL
002aac729
Measurement points are given in Table 8.
VOL and VOH are typical voltage output drop that occur with
the output load.
Figure 8. CP to Yn propagation delays, clock pulse
width, and maximum clock frequency
OE input
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
VM
tPLZ
tPHZ
outputs
enabled
VI
tPZL
VX
VY
tPZH
outputs
disabled
GND
VCC
VM
VOL
VOH
VM
GND
outputs
enabled
002aac731
Measurement points are given in Table 8.
VOL and VOH are typical voltage output drop that occur with
the output load.
Figure 10. 3-state enable and disable times
Table 8. Measurement points
Supply voltage Input
VCC
VI
≤ 2.3 V
VCC
2.3 V to 2.7 V
2.7 V
VCC
2.7 V
3.0 V to 3.6 V
2.7 V
VM
0.5 x VCC
0.5 x VCC
1.5 V
1.5 V
Output
VM
0.5 x VCC
0.5 x VCC
1.5 V
1.5 V
VX
VOL + 0.15 V
VOL + 0.15 V
VOL + 0.3 V
VOL + 0.3 V
VY
VOH - 0.15 V
VOH - 0.15 V
VOH - 0.3 V
VOH - 0.3 V
74ALVC16834A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 21 November 2017
© Nexperia B.V. 2017. All rights reserved.
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