IDT7026L20J Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT7026L20J Datasheet PDF : 18 Pages
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IDT7026S/L
High-Speed 16K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5)
tWC
ADDR"A"
MATCH
tWP
R/W"A"
tDW
tDH
DATAIN "A"
tAPS (1)
VALID
ADDR"B"
BUSY"B"
tBAA
MATCH
tBDA
tBDD
tWDD
DATAOUT "B"
tDDD (3)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
VALID
2939 drw 12
Timing Waveform of Write with BUSY (M/S = VIL)
tWP
R/W"A"
BUSY"B"
tWB(3)
tWH (1)
R/W"B"
(2)
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the “SLAVE” version.
,
2939 drw 13
61.432
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