IDT7026L25J(1996) Ver la hoja de datos (PDF) - Integrated Device Technology

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IDT7026L25J
(Rev.:1996)

HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7026S/L

HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM

WAVEFORM OF READ CYCLES(5)

tRC

ADDR

CE

tAA (4)

tACE (4)

tAOE (4)

OE

, UB LB

tABE (4)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

R/W

DATAOUT

tLZ (1)

tOH

VALID DATA(4)

BUSYOUT

tBDD (3, 4)

tHZ (2)

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NOTES:

1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.

2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations

BUSY has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

TIMING OF POWER-UP POWER-DOWN

CE

tPU

ICC

50%

ISB

tPD

50%

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6.17

8

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