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ST7263BK4 Ver la hoja de datos (PDF) - STMicroelectronics

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ST7263BK4 Datasheet PDF : 186 Pages
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ST7263Bxx
2
Pin description
Pin description
2.1
Note:
2.2
RESET signal (bidirectional)
It is active low and forces the initialization of the MCU. This event is the top priority non
maskable interrupt. This pin is switched low when the Watchdog is triggered or the VDD is
low. It can be used to reset external peripherals.
Adding two 100 nF decoupling capacitors on the Reset pin (respectively connected to VDD
and VSS) will significantly improve product electromagnetic susceptibility performance.
OSCIN/OSCOUT: input/output oscillator pin
These pins connect a parallel-resonant crystal, or an external source, to the on-chip
oscillator.
2.3
Note:
VDD/VSS
Main power supply and ground voltages
To enhance the reliability of operation, it is recommended that VDDA and VDD be connected
together on the application board. This also applies to VSSA and VSS.
2.4
Note:
VDDA/VSSA
Power supply and ground voltages for analog peripherals.
To enhance the reliability of operation, it is recommended that VDDA and VDD be connected
together on the application board. This also applies to VSSA and VSS.
2.5
Alternate functions
Several pins of the I/O ports assume software programmable alternate functions as shown
in the pin description.
Note: 1 The USBOE alternate function is mapped on Port C2 in 32/34/48 pin devices. In SO24
devices it is mapped on Port B1.
2 The timer OCMP1 alternate function is mapped on Port A6 in 32/34/48 pin devices. In SO24
devices it is not available.
Doc ID 7516 Rev 8
13/186

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